| Message ID | 20200724111846.24432-1-gregor.herburger@ew.tq-group.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/1] edac: fsl_ddr_edac: fix expected data message | expand |
On Fri, Jul 24, 2020 at 01:18:46PM +0200, Gregor Herburger wrote: > In some cases a wrong 'Expected Data' is calculated and reported. In some cases? Which cases? You need to expand that sentence with more details as to what the problem is because I'm not getting any smarter from it. > When comparing Expected/Captured Data this looks like dual bit errors when > only a single bit error occurred. > > On my aarch64 machine it prints something similar to this: > [ 311.103794] EDAC FSL_DDR MC0: Faulty Data bit: 36 > [ 311.108490] EDAC FSL_DDR MC0: Expected Data / ECC: 0xffffffef_ffffffff / 0x80000059 > [ 311.116135] EDAC FSL_DDR MC0: Captured Data / ECC: 0xffffffff_ffffffef / 0x59 Is that output before or after your change? 0xffffffef is with bit 4 XORed and cap_high was -1 before, cap_low is -1 too. The expected data syndrome has bit 31 set?! Yeah, I'm confused. Please explain the issue in greater detail, try structuring it this way: Problem is A. It happens because of B. Fix it by doing C. (Potentially do D). For more detailed info, see Documentation/process/submitting-patches.rst, Section "2) Describe your changes". Thx.
diff --git a/drivers/edac/fsl_ddr_edac.c b/drivers/edac/fsl_ddr_edac.c index 6d8ea226010d..4b6989cf1947 100644 --- a/drivers/edac/fsl_ddr_edac.c +++ b/drivers/edac/fsl_ddr_edac.c @@ -343,9 +343,9 @@ static void fsl_mc_check(struct mem_ctl_info *mci) fsl_mc_printk(mci, KERN_ERR, "Expected Data / ECC:\t%#8.8x_%08x / %#2.2x\n", - cap_high ^ (1 << (bad_data_bit - 32)), - cap_low ^ (1 << bad_data_bit), - syndrome ^ (1 << bad_ecc_bit)); + (bad_data_bit > 31) ? cap_high ^ (1 << (bad_data_bit - 32)) : cap_high, + (bad_data_bit <= 31) ? cap_low ^ (1 << (bad_data_bit)) : cap_low, + (bad_ecc_bit != -1) ? syndrome ^ (1 << (bad_ecc_bit)) : syndrome); } fsl_mc_printk(mci, KERN_ERR,
In some cases a wrong 'Expected Data' is calculated and reported. When comparing Expected/Captured Data this looks like dual bit errors when only a single bit error occurred. On my aarch64 machine it prints something similar to this: [ 311.103794] EDAC FSL_DDR MC0: Faulty Data bit: 36 [ 311.108490] EDAC FSL_DDR MC0: Expected Data / ECC: 0xffffffef_ffffffff / 0x80000059 [ 311.116135] EDAC FSL_DDR MC0: Captured Data / ECC: 0xffffffff_ffffffef / 0x59 Fix this by only shift the register where the error occurred. Signed-off-by: Gregor Herburger <gregor.herburger@ew.tq-group.com> --- drivers/edac/fsl_ddr_edac.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)