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Wed, 23 Jun 2021 19:20:36 +0000 From: Yazen Ghannam To: linux-edac@vger.kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, mchehab@kernel.org, tony.luck@intel.com, Smita.KoralahalliChannabasappa@amd.com, Yazen Ghannam , x86@kernel.org Subject: [PATCH v2 02/31] x86/amd_nb, EDAC/amd64: Move DF Indirect Read to AMD64 EDAC Date: Wed, 23 Jun 2021 19:19:33 +0000 Message-Id: <20210623192002.3671647-3-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210623192002.3671647-1-yazen.ghannam@amd.com> References: <20210623192002.3671647-1-yazen.ghannam@amd.com> X-Originating-IP: [165.204.184.1] X-ClientProxiedBy: BLAPR03CA0107.namprd03.prod.outlook.com (2603:10b6:208:32a::22) To BN8PR12MB3108.namprd12.prod.outlook.com (2603:10b6:408:40::20) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from yaz-ethanolx.amd.com (165.204.184.1) by BLAPR03CA0107.namprd03.prod.outlook.com (2603:10b6:208:32a::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.19 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: WQy3b52S+gUaAnNOH/h4F7yWi7D8wNY0ytlzF3W2IdXVRXsryyRlk/dbAL5tILVAFezeg8bUaem4AXuke7CSQLZ1NbiSfZJ1F9RlP2BNJu4su4C2pyC36uxfHfR63fySLzRRGW7du0kfQg/hIN74Typomn4etrobf7atgRdecKYN/+LXQYoi9vG03wxX/IZJs7+dEIFDlJxmIJFTtZyKqv4CeKqaaaJjDeFROi/LxOBFtTemSseL0TPJtX66Byz3uEo+vupk+zN0ik/jN4MVYEfWoihpeRq2nL1ydr1YkoNXL47NIlGO0VbS0bs+Yytp70cO7hofVxvX6nnG28ynlQlOmaGZxgXEt9y8FRcJPKXitxI0k8TtZ2CEYF+d0mfoOEN3yuQMu1kToAQQYHy1s2VLuFDEjtwYqZwFttKaNyJvtt2uuzZyd6Hs/ZnWpVzWO4m9/dsvfXqEE80Q10olUTaaMbkio8g1t6uCQkSNievyk5cVKlNrFE4tFXxUlTyl5mtgTuLE1jo9FEqxtE/dq6EigPzcIKeyGZSHoqBBe9QzGyfcodEsYwP6Up38DtCt9Kxqh4vHRaZAzAcclz7i8hcSVR54AINu+FBWM2h+kO75C+/OeIXF2TyAr+sgzqGaNZHxF5JJAaq82qrs6a8tr/wmudZWsqYgVdJKsCUAnf3Qcf5KW7WNVqa91nKhAzht4jP9aP5LOUYw4unCMfXKI0m8HvwZthe43WrEM5s7wseK+igWORrEr5WmXX5Z4YM8fDQbOzvxZmymuGWdCjR9cWbldOY5I7IGg9p4kdO+vL36jT7nFkhjhony2bBYzOmwbTNSfyTvuOCCuwnATsQ8PXm8dWlkfs8TNihrxj6RxNRDNcvkMaTNYAXP2ZSQ8r3eNaoJliOGYQrJ9ykOwCjURJgKj3upCYxBW8eyuBdndT8zQ6467F6iXaPaTGjG5aBfWgutcWMAlOkNEV2JpHXh5/zUKmUlSfS8HyQeDKNzPZJKdJCl8+bs8Bdvhtxf7GDPAEjEB/PGNx7RPx4Qc4PQCcPLqgSwtRhoImiTNRtFG5jOpySnaEzeAPpxFOekjB8IZcOl/V49jef0i0zriaTkuZYAGu8NRXtFY6dfiwW6tMwBGLzedea7WJaIgUuo8IDwSXjXT+3Rw4IilR4deg/V2qnopsjXp5G+w387NwOysYBRaVnqCNRxeBKkMUpZO//qi1s4QA+Mpp78D16gH1jI5VGC+ChpTEmjYhFdZjda2vU7mCP2FTn36QGxU5A0jMXNiMxHJc6n7pHYn+1SIkot3qn9RN9dQ5hy7RLtK5jBH29GfIro8qqkSMPAKKHfp2lU X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: e14d03bf-5fa1-49c7-da3d-08d9367bfad4 X-MS-Exchange-CrossTenant-AuthSource: BN8PR12MB3108.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jun 2021 19:20:36.8225 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: NTdCxOee/ypNsIRmbwJ0opmcbC7Il57OHTrEAiIaAWiFPTSW1P0Ci/MRzKHtWJISYKExeYao2xm3rnBv5jk8PA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1187 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The df_indirect_read() function is only used for address translation. Move this to EDAC along with the translation code. Cc: Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/YKJoICQzD/o7ZPBp@zn.tnic v1->v2: * New in v2. arch/x86/include/asm/amd_nb.h | 1 - arch/x86/kernel/amd_nb.c | 50 +---------------------------------- drivers/edac/amd64_edac.c | 50 +++++++++++++++++++++++++++++++++++ 3 files changed, 51 insertions(+), 50 deletions(-) diff --git a/arch/x86/include/asm/amd_nb.h b/arch/x86/include/asm/amd_nb.h index 455066a06f60..00d1a400b7a1 100644 --- a/arch/x86/include/asm/amd_nb.h +++ b/arch/x86/include/asm/amd_nb.h @@ -24,7 +24,6 @@ extern int amd_set_subcaches(int, unsigned long); extern int amd_smn_read(u16 node, u32 address, u32 *value); extern int amd_smn_write(u16 node, u32 address, u32 value); -extern int amd_df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo); struct amd_l3_cache { unsigned indices; diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c index 23dda362dc0f..5884dfa619ff 100644 --- a/arch/x86/kernel/amd_nb.c +++ b/arch/x86/kernel/amd_nb.c @@ -27,7 +27,7 @@ #define PCI_DEVICE_ID_AMD_19H_DF_F4 0x1654 #define PCI_DEVICE_ID_AMD_19H_M50H_DF_F4 0x166e -/* Protect the PCI config register pairs used for SMN and DF indirect access. */ +/* Protect the PCI config register pairs used for SMN. */ static DEFINE_MUTEX(smn_mutex); static u32 *flush_words; @@ -177,54 +177,6 @@ int amd_smn_write(u16 node, u32 address, u32 value) } EXPORT_SYMBOL_GPL(amd_smn_write); -/* - * Data Fabric Indirect Access uses FICAA/FICAD. - * - * Fabric Indirect Configuration Access Address (FICAA): Constructed based - * on the device's Instance Id and the PCI function and register offset of - * the desired register. - * - * Fabric Indirect Configuration Access Data (FICAD): There are FICAD LO - * and FICAD HI registers but so far we only need the LO register. - */ -int amd_df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo) -{ - struct pci_dev *F4; - u32 ficaa; - int err = -ENODEV; - - if (node >= amd_northbridges.num) - goto out; - - F4 = node_to_amd_nb(node)->link; - if (!F4) - goto out; - - ficaa = 1; - ficaa |= reg & 0x3FC; - ficaa |= (func & 0x7) << 11; - ficaa |= instance_id << 16; - - mutex_lock(&smn_mutex); - - err = pci_write_config_dword(F4, 0x5C, ficaa); - if (err) { - pr_warn("Error writing DF Indirect FICAA, FICAA=0x%x\n", ficaa); - goto out_unlock; - } - - err = pci_read_config_dword(F4, 0x98, lo); - if (err) - pr_warn("Error reading DF Indirect FICAD LO, FICAA=0x%x.\n", ficaa); - -out_unlock: - mutex_unlock(&smn_mutex); - -out: - return err; -} -EXPORT_SYMBOL_GPL(amd_df_indirect_read); - int amd_cache_northbridges(void) { const struct pci_device_id *misc_ids = amd_nb_misc_ids; diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 046b98fcc4fe..e9342d7d693f 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -993,6 +993,56 @@ static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr) return csrow; } +/* Protect the PCI config register pairs used for DF indirect access. */ +static DEFINE_MUTEX(df_indirect_mutex); + +/* + * Data Fabric Indirect Access uses FICAA/FICAD. + * + * Fabric Indirect Configuration Access Address (FICAA): Constructed based + * on the device's Instance Id and the PCI function and register offset of + * the desired register. + * + * Fabric Indirect Configuration Access Data (FICAD): There are FICAD LO + * and FICAD HI registers but so far we only need the LO register. + */ +static int amd_df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo) +{ + struct pci_dev *F4; + u32 ficaa; + int err = -ENODEV; + + if (node >= amd_nb_num()) + goto out; + + F4 = node_to_amd_nb(node)->link; + if (!F4) + goto out; + + ficaa = 1; + ficaa |= reg & 0x3FC; + ficaa |= (func & 0x7) << 11; + ficaa |= instance_id << 16; + + mutex_lock(&df_indirect_mutex); + + err = pci_write_config_dword(F4, 0x5C, ficaa); + if (err) { + pr_warn("Error writing DF Indirect FICAA, FICAA=0x%x\n", ficaa); + goto out_unlock; + } + + err = pci_read_config_dword(F4, 0x98, lo); + if (err) + pr_warn("Error reading DF Indirect FICAD LO, FICAA=0x%x.\n", ficaa); + +out_unlock: + mutex_unlock(&df_indirect_mutex); + +out: + return err; +} + static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { u64 dram_base_addr, dram_limit_addr, dram_hole_base;