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Wed, 23 Jun 2021 19:20:40 +0000 From: Yazen Ghannam To: linux-edac@vger.kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, mchehab@kernel.org, tony.luck@intel.com, Smita.KoralahalliChannabasappa@amd.com, Yazen Ghannam Subject: [PATCH v2 03/31] EDAC/amd64: Don't use naked values for DF registers Date: Wed, 23 Jun 2021 19:19:34 +0000 Message-Id: <20210623192002.3671647-4-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210623192002.3671647-1-yazen.ghannam@amd.com> References: <20210623192002.3671647-1-yazen.ghannam@amd.com> X-Originating-IP: [165.204.184.1] X-ClientProxiedBy: BLAPR03CA0107.namprd03.prod.outlook.com (2603:10b6:208:32a::22) To BN8PR12MB3108.namprd12.prod.outlook.com (2603:10b6:408:40::20) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from yaz-ethanolx.amd.com (165.204.184.1) by BLAPR03CA0107.namprd03.prod.outlook.com (2603:10b6:208:32a::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4242.19 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: K0aiUdBaZgjvE1yxJQxyWpGX50Qs3KIj63NXvmeleIgPdKze6/ZTrEmfFZLs+RTs2mSeaBtqjgtjMAEWe02FQaqdvXkKPnrKxOSorlqUE+Aaom9fsPkLztVeaueJracZ4+3an1x9hY1cStfrcHeKjShrrrIFvOnH7hMli8LuhBdKdJjEiBfQ9Kr4++uwR2dZ9ZiJvKW28oAmk67eXQTiFsW9gMcKTso7+IyHPUIs6Gc4CNd8cWykU0s4fXF46VV1neXU5Lnpm55i2hO6lM8bki2qOC2K0W1k7HCcJ8YlbXeJofO01cTCm8cAeOEPVo+An/D4lTujzeczkMrug17X6KywfSJAoC7eS56Epe9GGuUBVDWJMK8fFhZMAoLRf+XqueTmXYPTARIzH5i+Klop4XgXk2bfFXjdY5ZDwpyVNxDTWgqoNx5IMu/LGUw9PVzD9d84INIgMSnsH/SI9O3jGDZ27NHxQtDk4GKf2yL4/0of4227a6fVZr1xayFZkWMOT3LyTN9Lib4mSPl6Buvw0Beh/8EU1oD7/r6dm3J8bYQ0A89QSJwxM1Y6bXjoTXuHHft7xaBzEwIYwz4PUoTeH5EyMdyNMj+Ov6WglBd8Ak+Ws6823kC4DE/++mbmByWh8eImb4m38pKZPcDG4LDqRA2Y5NTUIsXvPfVqMeTTu8BizofYvklh3f9bDSS3Z19ktN3iml7teXrCR48V/Nwm3L0TQKDSbMdqpSGDPO3h64+pr1pEdRX+l4oUyrFPg6dVzcloappH7QsDa1iFdg/qFooznqE+/XpW0e67JuChHnc1txeKF9zigNu+pcKsmuO+OyBHo600j+elZU5vVy/nwvohDXV4NmkDYTaYwTRyP4YVAwxF4kjboOyfEVmHnvR7FDJNFu1uv1xaf9+RaWkXyreQpIRV8S9FJgbiBr23Sh2fg/OVUBPRNmWEHufKpuIphntlq7JDe6t/xdDybvkiNI30wrefAMkpvbAf2P/a/UPOk5eR1hyA4xmd9Z1nKABG4AYEDfYx7uTFIdyzWtCjDN2yQ136CGIavj4fkabWBm1FGeDiJeLO4yLLKgSPuf5VaF7PYiuJxPHOJG66yU1iG+DGDAGHctEbvqLPa3og99jLS06178foTyeeflt35Wlt4pbxb8xfoKXb+0psXq/pb+0R3RGTO5s662gP+jbBpb6SYKl56R2MKqHuEUH56tXuEvG3BLFm99C3wuW7nS3+bzrENG6jddFWml5Ry681ub0h5oUZ9pILEc2L/jZyxIjjcPFtpt6TJrDwdCJ6qJ6wNRjMsVr5at1h5mMoDDRlUTpDZh82BBowvZHGe7SbcECZ X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: a0e7ce57-58c4-404e-ff1d-08d9367bfcd7 X-MS-Exchange-CrossTenant-AuthSource: BN8PR12MB3108.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Jun 2021 19:20:40.1966 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: QvfExIq6L1CvoDDA7ZJAAVCoONXwByLDFTL6e2tmb9tMLpYyqDvcgqJG2/m9p5nsKUMVgQsahitbbEhGu7qI0Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1187 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org AMD Data Fabric registers are defined using a combination of PCI function number and offset. Define a struct to hold these values, and update the DF Indirect Access function to accept a struct of this type. Update the address translation code to include a list of the needed DF registers using this new format. Define an enumeration to give the registers more human-readable names. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20210507190140.18854-2-Yazen.Ghannam@amd.com v1->v2: * Moved from arch/x86 to EDAC. drivers/edac/amd64_edac.c | 60 ++++++++++++++++++++++++++++++--------- 1 file changed, 47 insertions(+), 13 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index e9342d7d693f..b94067e3952b 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -996,6 +996,11 @@ static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr) /* Protect the PCI config register pairs used for DF indirect access. */ static DEFINE_MUTEX(df_indirect_mutex); +struct df_reg { + u8 func; + u16 offset; +}; + /* * Data Fabric Indirect Access uses FICAA/FICAD. * @@ -1006,7 +1011,7 @@ static DEFINE_MUTEX(df_indirect_mutex); * Fabric Indirect Configuration Access Data (FICAD): There are FICAD LO * and FICAD HI registers but so far we only need the LO register. */ -static int amd_df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo) +static int amd_df_indirect_read(u16 node, struct df_reg reg, u8 instance_id, u32 *lo) { struct pci_dev *F4; u32 ficaa; @@ -1020,8 +1025,8 @@ static int amd_df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 goto out; ficaa = 1; - ficaa |= reg & 0x3FC; - ficaa |= (func & 0x7) << 11; + ficaa |= reg.offset & 0x3FC; + ficaa |= (reg.func & 0x7) << 11; ficaa |= instance_id << 16; mutex_lock(&df_indirect_mutex); @@ -1043,6 +1048,33 @@ static int amd_df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 return err; } +enum df_reg_names { + /* Function 0 */ + FAB_BLK_INST_INFO_3, + DRAM_HOLE_CTL, + DRAM_BASE_ADDR, + DRAM_LIMIT_ADDR, + DRAM_OFFSET, + + /* Function 1 */ + SYS_FAB_ID_MASK, +}; + +static struct df_reg df_regs[] = { + /* D18F0x50 (FabricBlockInstanceInformation3_CS) */ + [FAB_BLK_INST_INFO_3] = {0, 0x50}, + /* D18F0x104 (DramHoleControl) */ + [DRAM_HOLE_CTL] = {0, 0x104}, + /* D18F0x110 (DramBaseAddress) */ + [DRAM_BASE_ADDR] = {0, 0x110}, + /* D18F0x114 (DramLimitAddress) */ + [DRAM_LIMIT_ADDR] = {0, 0x114}, + /* D18F0x1B4 (DramOffset) */ + [DRAM_OFFSET] = {0, 0x1B4}, + /* D18F1x208 (SystemFabricIdMask) */ + [SYS_FAB_ID_MASK] = {1, 0x208}, +}; + static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { u64 dram_base_addr, dram_limit_addr, dram_hole_base; @@ -1059,8 +1091,9 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr u8 cs_mask, cs_id = 0; bool hash_enabled = false; - /* Read D18F0x1B4 (DramOffset), check if base 1 is used. */ - if (amd_df_indirect_read(nid, 0, 0x1B4, umc, &tmp)) + struct df_reg reg; + + if (amd_df_indirect_read(nid, df_regs[DRAM_OFFSET], umc, &tmp)) goto out_err; /* Remove HiAddrOffset from normalized address, if enabled: */ @@ -1073,8 +1106,9 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr } } - /* Read D18F0x110 (DramBaseAddress). */ - if (amd_df_indirect_read(nid, 0, 0x110 + (8 * base), umc, &tmp)) + reg = df_regs[DRAM_BASE_ADDR]; + reg.offset += base * 8; + if (amd_df_indirect_read(nid, reg, umc, &tmp)) goto out_err; /* Check if address range is valid. */ @@ -1096,8 +1130,9 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr goto out_err; } - /* Read D18F0x114 (DramLimitAddress). */ - if (amd_df_indirect_read(nid, 0, 0x114 + (8 * base), umc, &tmp)) + reg = df_regs[DRAM_LIMIT_ADDR]; + reg.offset += base * 8; + if (amd_df_indirect_read(nid, reg, umc, &tmp)) goto out_err; intlv_num_sockets = (tmp >> 8) & 0x1; @@ -1153,7 +1188,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr * umc/channel# as instance id of the coherent slave * for FICAA. */ - if (amd_df_indirect_read(nid, 0, 0x50, umc, &tmp)) + if (amd_df_indirect_read(nid, df_regs[FAB_BLK_INST_INFO_3], umc, &tmp)) goto out_err; cs_fabric_id = (tmp >> 8) & 0xFF; @@ -1168,9 +1203,8 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr sock_id_bit = die_id_bit; - /* Read D18F1x208 (SystemFabricIdMask). */ if (intlv_num_dies || intlv_num_sockets) - if (amd_df_indirect_read(nid, 1, 0x208, umc, &tmp)) + if (amd_df_indirect_read(nid, df_regs[SYS_FAB_ID_MASK], umc, &tmp)) goto out_err; /* If interleaved over more than 1 die. */ @@ -1209,7 +1243,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr /* If legacy MMIO hole enabled */ if (lgcy_mmio_hole_en) { - if (amd_df_indirect_read(nid, 0, 0x104, umc, &tmp)) + if (amd_df_indirect_read(nid, df_regs[DRAM_HOLE_CTL], umc, &tmp)) goto out_err; dram_hole_base = tmp & GENMASK(31, 24);