| Message ID | 20211219223127.71554-1-m@zorinaq.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | EDAC/amd64: Add PCI device IDs for family 19h model 50h | expand |
On Sun, Dec 19, 2021 at 02:31:27PM -0800, Marc Bevand wrote: > Add the new family 19h model 50h PCI IDs (device 18h functions 0 and 6) > to support Ryzen 5000 APUs ("Cezanne"). > > Signed-off-by: Marc Bevand <m@zorinaq.com> Hi Marc, Thanks for the patch. > --- > drivers/edac/amd64_edac.c | 16 ++++++++++++++++ > drivers/edac/amd64_edac.h | 3 +++ > 2 files changed, 19 insertions(+) > There are some recent changes in these files upstream. So this patch won't apply. Can you please base this patch on the following branch? https://git.kernel.org/pub/scm/linux/kernel/git/ras/ras.git/log/?h=edac-for-next > diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c > index 4fce75013674..45c81c0a232f 100644 > --- a/drivers/edac/amd64_edac.c > +++ b/drivers/edac/amd64_edac.c > @@ -2650,6 +2650,16 @@ static struct amd64_family_type family_types[] = { > .dbam_to_cs = f17_addr_mask_to_cs_size, > } > }, > + [F19_M50H_CPUS] = { > + .ctl_name = "F19h_M50h", > + .f0_id = PCI_DEVICE_ID_AMD_19H_M50H_DF_F0, > + .f6_id = PCI_DEVICE_ID_AMD_19H_M50H_DF_F6, > + .max_mcs = 2, > + .ops = { > + .early_channel_count = f17_early_channel_count, > + .dbam_to_cs = f17_addr_mask_to_cs_size, > + } > + }, > }; > > /* > @@ -3693,6 +3703,12 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt) > fam_type->ctl_name = "F19h_M20h"; > break; > } > + if (pvt->model == 0x50) { AMD systems are generally released in model groups. So this change should apply to models 0x50 to 0x5f inclusive. When updating this patch, you should find that there some "if/else if" statements for the various model groups sorted in ascending order. This addition should be inserted there. > + fam_type = &family_types[F19_M50H_CPUS]; > + pvt->ops = &family_types[F19_M50H_CPUS].ops; > + fam_type->ctl_name = "F19h_M50h"; > + break; > + } > fam_type = &family_types[F19_CPUS]; > pvt->ops = &family_types[F19_CPUS].ops; > family_types[F19_CPUS].ctl_name = "F19h"; > diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h > index 85aa820bc165..796e39e1890c 100644 > --- a/drivers/edac/amd64_edac.h > +++ b/drivers/edac/amd64_edac.h > @@ -126,6 +126,8 @@ > #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F6 0x1446 > #define PCI_DEVICE_ID_AMD_19H_DF_F0 0x1650 > #define PCI_DEVICE_ID_AMD_19H_DF_F6 0x1656 > +#define PCI_DEVICE_ID_AMD_19H_M50H_DF_F0 0x166a > +#define PCI_DEVICE_ID_AMD_19H_M50H_DF_F6 0x1670 > > /* > * Function 1 - Address Map > @@ -298,6 +300,7 @@ enum amd_families { > F17_M60H_CPUS, > F17_M70H_CPUS, > F19_CPUS, > + F19_M50H_CPUS, > NUM_FAMILIES, > }; > > -- Everything else looks good to me. Thanks, Yazen
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 4fce75013674..45c81c0a232f 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -2650,6 +2650,16 @@ static struct amd64_family_type family_types[] = { .dbam_to_cs = f17_addr_mask_to_cs_size, } }, + [F19_M50H_CPUS] = { + .ctl_name = "F19h_M50h", + .f0_id = PCI_DEVICE_ID_AMD_19H_M50H_DF_F0, + .f6_id = PCI_DEVICE_ID_AMD_19H_M50H_DF_F6, + .max_mcs = 2, + .ops = { + .early_channel_count = f17_early_channel_count, + .dbam_to_cs = f17_addr_mask_to_cs_size, + } + }, }; /* @@ -3693,6 +3703,12 @@ static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt) fam_type->ctl_name = "F19h_M20h"; break; } + if (pvt->model == 0x50) { + fam_type = &family_types[F19_M50H_CPUS]; + pvt->ops = &family_types[F19_M50H_CPUS].ops; + fam_type->ctl_name = "F19h_M50h"; + break; + } fam_type = &family_types[F19_CPUS]; pvt->ops = &family_types[F19_CPUS].ops; family_types[F19_CPUS].ctl_name = "F19h"; diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index 85aa820bc165..796e39e1890c 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -126,6 +126,8 @@ #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F6 0x1446 #define PCI_DEVICE_ID_AMD_19H_DF_F0 0x1650 #define PCI_DEVICE_ID_AMD_19H_DF_F6 0x1656 +#define PCI_DEVICE_ID_AMD_19H_M50H_DF_F0 0x166a +#define PCI_DEVICE_ID_AMD_19H_M50H_DF_F6 0x1670 /* * Function 1 - Address Map @@ -298,6 +300,7 @@ enum amd_families { F17_M60H_CPUS, F17_M70H_CPUS, F19_CPUS, + F19_M50H_CPUS, NUM_FAMILIES, };
Add the new family 19h model 50h PCI IDs (device 18h functions 0 and 6) to support Ryzen 5000 APUs ("Cezanne"). Signed-off-by: Marc Bevand <m@zorinaq.com> --- drivers/edac/amd64_edac.c | 16 ++++++++++++++++ drivers/edac/amd64_edac.h | 3 +++ 2 files changed, 19 insertions(+)