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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; Received: from SATLEXMB03.amd.com (165.204.84.17) by BN8NAM11FT039.mail.protection.outlook.com (10.13.177.169) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4823.18 via Frontend Transport; Tue, 28 Dec 2021 20:06:31 +0000 Received: from yaz-ethanolx.amd.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 28 Dec 2021 14:06:31 -0600 From: Yazen Ghannam To: CC: , , , , , , , , "Yazen Ghannam" Subject: [PATCH v3 1/2] EDAC/amd64: Set memory type per DIMM Date: Tue, 28 Dec 2021 20:06:14 +0000 Message-ID: <20211228200615.412999-2-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211228200615.412999-1-yazen.ghannam@amd.com> References: <20211228200615.412999-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB03.amd.com (10.181.40.144) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 360f4765-3d77-4431-2314-08d9ca3d8ac0 X-MS-TrafficTypeDiagnostic: MW3PR12MB4412:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:576; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Dec 2021 20:06:31.8830 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 360f4765-3d77-4431-2314-08d9ca3d8ac0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT039.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4412 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Current AMD systems allow mixing of DIMM types within a system. However, DIMMs within a channel, i.e. managed by a single Unified Memory Controller (UMC), must be of the same type. Handle this possible configuration by checking and setting the memory type for each individual EDAC "DIMM" structure. Signed-off-by: Yazen Ghannam --- Link: https://lkml.kernel.org/r/20211215155309.2711917-2-yazen.ghannam@amd.com v2->v3: * Change patch to properly handle systems with different DIMM types. v1->v2: * Was patch 3 in v1. * Update commit message. drivers/edac/amd64_edac.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index fba609ada0e6..4db92c77276f 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1616,19 +1616,23 @@ static void read_dct_base_mask(struct amd64_pvt *pvt) } } +static enum mem_type determine_memory_type_df(struct amd64_umc *umc) +{ + if (umc->dimm_cfg & BIT(5)) + return MEM_LRDDR4; + + if (umc->dimm_cfg & BIT(4)) + return MEM_RDDR4; + + return MEM_DDR4; +} + static void determine_memory_type(struct amd64_pvt *pvt) { u32 dram_ctrl, dcsm; - if (pvt->umc) { - if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(5)) - pvt->dram_type = MEM_LRDDR4; - else if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(4)) - pvt->dram_type = MEM_RDDR4; - else - pvt->dram_type = MEM_DDR4; + if (pvt->umc) return; - } switch (pvt->fam) { case 0xf: @@ -3547,8 +3551,8 @@ static int init_csrows_df(struct mem_ctl_info *mci) edac_dbg(1, "MC node: %d, csrow: %d\n", pvt->mc_node_id, cs); + dimm->mtype = determine_memory_type_df(&pvt->umc[umc]); dimm->nr_pages = get_csrow_nr_pages(pvt, umc, cs); - dimm->mtype = pvt->dram_type; dimm->edac_mode = edac_mode; dimm->dtype = dev_type; dimm->grain = 64;