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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT063.mail.protection.outlook.com (10.13.175.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4930.15 via Frontend Transport; Thu, 27 Jan 2022 20:41:40 +0000 Received: from yaz-ethanolx.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Thu, 27 Jan 2022 14:41:38 -0600 From: Yazen Ghannam To: CC: , , , , , , , Yazen Ghannam Subject: [PATCH v4 04/24] EDAC/amd64: Define function to find interleaving mode Date: Thu, 27 Jan 2022 20:40:55 +0000 Message-ID: <20220127204115.384161-5-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127204115.384161-1-yazen.ghannam@amd.com> References: <20220127204115.384161-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: edc86d2e-1077-44c4-37a7-08d9e1d56c14 X-MS-TrafficTypeDiagnostic: BN8PR12MB2995:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2201; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2022 20:41:40.5308 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: edc86d2e-1077-44c4-37a7-08d9e1d56c14 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB2995 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Define a helper function to find the interleaving mode. Define a DF2-specific function now. Future DF versions will have their own functions. Use an enumeration for the interleaving modes to give a human-readable value. Save the interleaving mode in the context struct, since this will be used in multiple functions. Multiple interleaving modes support hashing, so save a boolean in the context struct to check if hashing is enabled. This boolean will be replaced with a function pointer in a later patch. Signed-off-by: Yazen Ghannam --- Link: https://lore.kernel.org/r/20211028175728.121452-9-yazen.ghannam@amd.com v3->v4: * Remove leading whitespace in function pointer definition. * Include pr_debug() on failure. v2->v3: * Was patch 9 in v2. * Updated commit message. v1->v2: * Moved from arch/x86 to EDAC. * Add new function to data_fabric_ops. drivers/edac/amd64_edac.c | 37 ++++++++++++++++++++++++++++++++++--- 1 file changed, 34 insertions(+), 3 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index d1af1ce716f9..4e83a9be4724 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1057,8 +1057,16 @@ static int df_indirect_read_broadcast(u16 node, u8 func, u16 reg, u32 *lo) return __df_indirect_read(node, func, reg, DF_BROADCAST, lo); } +/* These are mapped 1:1 to the hardware values. Special cases are set at > 0x20. */ +enum intlv_modes { + NONE = 0x00, + NOHASH_2CH = 0x01, + DF2_HASH_2CH = 0x21, +}; + /* Use "reg_" prefix for raw register values. */ struct addr_ctx { + enum intlv_modes intlv_mode; u64 ret_addr; u32 tmp; u32 reg_dram_offset; @@ -1067,10 +1075,12 @@ struct addr_ctx { u16 nid; u8 inst_id; u8 map_num; + bool hash_enabled; }; struct data_fabric_ops { u64 (*get_hi_addr_offset)(struct addr_ctx *ctx); + int (*get_intlv_mode)(struct addr_ctx *ctx); }; static u64 get_hi_addr_offset_df2(struct addr_ctx *ctx) @@ -1078,8 +1088,26 @@ static u64 get_hi_addr_offset_df2(struct addr_ctx *ctx) return (ctx->reg_dram_offset & GENMASK_ULL(31, 20)) << 8; } +static int get_intlv_mode_df2(struct addr_ctx *ctx) +{ + ctx->intlv_mode = (ctx->reg_base_addr >> 4) & 0xF; + + if (ctx->intlv_mode == 8) { + ctx->intlv_mode = DF2_HASH_2CH; + ctx->hash_enabled = true; + } + + if (ctx->intlv_mode != NONE && + ctx->intlv_mode != NOHASH_2CH && + ctx->intlv_mode != DF2_HASH_2CH) + return -EINVAL; + + return 0; +} + struct data_fabric_ops df2_ops = { .get_hi_addr_offset = get_hi_addr_offset_df2, + .get_intlv_mode = get_intlv_mode_df2, }; struct data_fabric_ops *df_ops; @@ -1146,7 +1174,6 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr u8 num_intlv_bits, hashed_bit; u8 lgcy_mmio_hole_en; u8 cs_mask, cs_id = 0; - bool hash_enabled = false; struct addr_ctx ctx; @@ -1173,6 +1200,11 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr goto out_err; } + if (df_ops->get_intlv_mode(&ctx)) { + pr_debug("Failed to get interleave mode"); + goto out_err; + } + lgcy_mmio_hole_en = ctx.reg_base_addr & BIT(1); intlv_num_chan = (ctx.reg_base_addr >> 4) & 0xF; intlv_addr_sel = (ctx.reg_base_addr >> 8) & 0x7; @@ -1200,7 +1232,6 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr case 7: intlv_num_chan = 4; break; case 8: intlv_num_chan = 1; - hash_enabled = true; break; default: pr_err("%s: Invalid number of interleaved channels %d.\n", @@ -1302,7 +1333,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr ctx.ret_addr += (BIT_ULL(32) - dram_hole_base); } - if (hash_enabled) { + if (ctx.hash_enabled) { /* Save some parentheses and grab ls-bit at the end. */ hashed_bit = (ctx.ret_addr >> 12) ^ (ctx.ret_addr >> 18) ^