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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT063.mail.protection.outlook.com (10.13.175.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4930.15 via Frontend Transport; Thu, 27 Jan 2022 20:41:43 +0000 Received: from yaz-ethanolx.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Thu, 27 Jan 2022 14:41:39 -0600 From: Yazen Ghannam To: CC: , , , , , , , Yazen Ghannam Subject: [PATCH v4 07/24] EDAC/amd64: Define function to dehash address Date: Thu, 27 Jan 2022 20:40:58 +0000 Message-ID: <20220127204115.384161-8-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220127204115.384161-1-yazen.ghannam@amd.com> References: <20220127204115.384161-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4ca49c76-bbf1-4380-0727-08d9e1d56dd2 X-MS-TrafficTypeDiagnostic: MWHPR1201MB0206:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8273; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2022 20:41:43.4525 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4ca49c76-bbf1-4380-0727-08d9e1d56dd2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT063.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR1201MB0206 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Move the dehashing code into a separate helper function. Define a DF2-specific function for the current code. Specific helper functions will be added for future DF versions. The dehashing function used is based on the interleaving mode rather than the Data Fabric version. So save the function pointer in the context struct. The use of "df2" in the name of the current function is only because the interleaving mode using it only appears on Data Fabric 2 systems. Signed-off-by: Yazen Ghannam --- Link: https://lore.kernel.org/r/20211028175728.121452-12-yazen.ghannam@amd.com v3->v4: * Include pr_debug() on failure. v2->v3: * Was patch 12 in v2. v1->v2: * Moved from arch/x86 to EDAC. * Add new function pointer in ctx struct. drivers/edac/amd64_edac.c | 36 +++++++++++++++++++++--------------- 1 file changed, 21 insertions(+), 15 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 350204eadb27..da2d0d9ce406 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1077,7 +1077,7 @@ struct addr_ctx { u8 map_num; u8 intlv_addr_bit; u8 cs_id; - bool hash_enabled; + int (*dehash_addr)(struct addr_ctx *ctx); }; struct data_fabric_ops { @@ -1090,13 +1090,29 @@ static u64 get_hi_addr_offset_df2(struct addr_ctx *ctx) return (ctx->reg_dram_offset & GENMASK_ULL(31, 20)) << 8; } +static int dehash_addr_df2(struct addr_ctx *ctx) +{ + u8 hashed_bit = (ctx->ret_addr >> 12) ^ + (ctx->ret_addr >> 18) ^ + (ctx->ret_addr >> 21) ^ + (ctx->ret_addr >> 30) ^ + ctx->cs_id; + + hashed_bit &= BIT(0); + + if (hashed_bit != ((ctx->ret_addr >> ctx->intlv_addr_bit) & BIT(0))) + ctx->ret_addr ^= BIT(ctx->intlv_addr_bit); + + return 0; +} + static int get_intlv_mode_df2(struct addr_ctx *ctx) { ctx->intlv_mode = (ctx->reg_base_addr >> 4) & 0xF; if (ctx->intlv_mode == 8) { ctx->intlv_mode = DF2_HASH_2CH; - ctx->hash_enabled = true; + ctx->dehash_addr = dehash_addr_df2; } if (ctx->intlv_mode != NONE && @@ -1313,7 +1329,6 @@ static int add_base_and_hole(struct addr_ctx *ctx) static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr) { u64 dram_limit_addr; - u8 hashed_bit; struct addr_ctx ctx; @@ -1357,18 +1372,9 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr goto out_err; } - if (ctx.hash_enabled) { - /* Save some parentheses and grab ls-bit at the end. */ - hashed_bit = (ctx.ret_addr >> 12) ^ - (ctx.ret_addr >> 18) ^ - (ctx.ret_addr >> 21) ^ - (ctx.ret_addr >> 30) ^ - ctx.cs_id; - - hashed_bit &= BIT(0); - - if (hashed_bit != ((ctx.ret_addr >> ctx.intlv_addr_bit) & BIT(0))) - ctx.ret_addr ^= BIT(ctx.intlv_addr_bit); + if (ctx.dehash_addr && ctx.dehash_addr(&ctx)) { + pr_debug("Failed to dehash address"); + goto out_err; } /* Is calculated system address is above DRAM limit address? */