diff mbox series

[09/18] EDAC/amd64: Add get_ecc_sym_sz() into pvt->ops

Message ID 20220509145534.44912-10-yazen.ghannam@amd.com (mailing list archive)
State New, archived
Headers show
Series AMD64 EDAC Cleanup and Refactor | expand

Commit Message

Yazen Ghannam May 9, 2022, 2:55 p.m. UTC 
From: Muralidhara M K <muralidhara.mk@amd.com>

GPU Nodes will need to determine ECC symbol size differently than
existing systems. A function pointer should be used rather than
introduce another branching condition.

Prepare for this by adding get_ecc_sym_sz() to pvt->ops and set it as
needed based on currently supported systems.

Use a "umc" prefix for modern systems, since these use Unified Memory
Controllers (UMCs).

Use a "dct" prefix for newly-defined legacy functions, since these
systems use DRAM Controllers (DCTs).

Signed-off-by: Muralidhara M K <muralidhara.mk@amd.com>
Signed-off-by: Naveen Krishna Chatradhi <naveenkrishna.chatradhi@amd.com>
[Rebased/reworked patch and reworded commit message]
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
 drivers/edac/amd64_edac.c | 43 +++++++++++++++++++++++----------------
 drivers/edac/amd64_edac.h |  1 +
 2 files changed, 26 insertions(+), 18 deletions(-)
diff mbox series

Patch

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index a767d8a6bfe8..2a3205f1205e 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -3169,26 +3169,11 @@  static void free_mc_sibling_devs(struct amd64_pvt *pvt)
 	}
 }
 
-static void determine_ecc_sym_sz(struct amd64_pvt *pvt)
+static void dct_determine_ecc_sym_sz(struct amd64_pvt *pvt)
 {
 	pvt->ecc_sym_sz = 4;
 
-	if (pvt->umc) {
-		u8 i;
-
-		for_each_umc(i) {
-			/* Check enabled channels only: */
-			if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) {
-				if (pvt->umc[i].ecc_ctrl & BIT(9)) {
-					pvt->ecc_sym_sz = 16;
-					return;
-				} else if (pvt->umc[i].ecc_ctrl & BIT(7)) {
-					pvt->ecc_sym_sz = 8;
-					return;
-				}
-			}
-		}
-	} else if (pvt->fam >= 0x10) {
+	if (pvt->fam >= 0x10) {
 		u32 tmp;
 
 		amd64_read_pci_cfg(pvt->F3, EXT_NB_MCA_CFG, &tmp);
@@ -3202,6 +3187,26 @@  static void determine_ecc_sym_sz(struct amd64_pvt *pvt)
 	}
 }
 
+static void umc_determine_ecc_sym_sz(struct amd64_pvt *pvt)
+{
+	u8 i;
+
+	pvt->ecc_sym_sz = 4;
+
+	for_each_umc(i) {
+		/* Check enabled channels only: */
+		if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) {
+			if (pvt->umc[i].ecc_ctrl & BIT(9)) {
+				pvt->ecc_sym_sz = 16;
+				return;
+			} else if (pvt->umc[i].ecc_ctrl & BIT(7)) {
+				pvt->ecc_sym_sz = 8;
+				return;
+			}
+		}
+	}
+}
+
 /*
  * Retrieve the hardware registers of the memory controller.
  */
@@ -3303,7 +3308,7 @@  static void read_mc_regs(struct amd64_pvt *pvt)
 
 	pvt->ops->determine_memory_type(pvt);
 
-	determine_ecc_sym_sz(pvt);
+	pvt->ops->determine_ecc_sym_sz(pvt);
 }
 
 /*
@@ -3760,6 +3765,7 @@  static struct low_ops umc_ops = {
 	.prep_chip_selects		= umc_prep_chip_selects,
 	.read_base_mask			= umc_read_base_mask,
 	.determine_memory_type		= umc_determine_memory_type,
+	.determine_ecc_sym_sz		= umc_determine_ecc_sym_sz,
 };
 
 /* Use Family 16h versions for defaults and adjust as needed below. */
@@ -3770,6 +3776,7 @@  static struct low_ops dct_ops = {
 	.prep_chip_selects		= dct_prep_chip_selects,
 	.read_base_mask			= dct_read_base_mask,
 	.determine_memory_type		= dct_determine_memory_type,
+	.determine_ecc_sym_sz		= dct_determine_ecc_sym_sz,
 };
 
 static int per_family_init(struct amd64_pvt *pvt)
diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
index da3db0f4f59b..5e9ff6ea7ebc 100644
--- a/drivers/edac/amd64_edac.h
+++ b/drivers/edac/amd64_edac.h
@@ -471,6 +471,7 @@  struct low_ops {
 	void (*prep_chip_selects)(struct amd64_pvt *pvt);
 	void (*read_base_mask)(struct amd64_pvt *pvt);
 	void (*determine_memory_type)(struct amd64_pvt *pvt);
+	void (*determine_ecc_sym_sz)(struct amd64_pvt *pvt);
 };
 
 int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,