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Mon, 9 May 2022 14:55:57 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT064.mail.protection.outlook.com (10.13.175.77) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5227.15 via Frontend Transport; Mon, 9 May 2022 14:55:57 +0000 Received: from yaz-ethanolx.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Mon, 9 May 2022 09:55:50 -0500 From: Yazen Ghannam To: , CC: , , , , Yazen Ghannam Subject: [PATCH 13/18] EDAC/amd64: Add determine_edac_ctl_cap() into pvt->ops Date: Mon, 9 May 2022 14:55:29 +0000 Message-ID: <20220509145534.44912-14-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509145534.44912-1-yazen.ghannam@amd.com> References: <20220509145534.44912-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e54ee8e9-0352-4282-47ba-08da31cc0686 X-MS-TrafficTypeDiagnostic: BN6PR12MB1409:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 May 2022 14:55:57.7024 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e54ee8e9-0352-4282-47ba-08da31cc0686 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT064.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1409 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Muralidhara M K GPU Nodes will have different criteria for checking the EDAC capabilities of a controller. A function pointer should be used rather than introduce another branching condition. Prepare for this by adding determine_edac_ctl_cap() to pvt->ops and set it as needed based on currently supported systems. Use a "umc" prefix for modern systems, since these use Unified Memory Controllers (UMCs). Use a "dct" prefix for newly-defined legacy functions, since these systems use DRAM Controllers (DCTs). Signed-off-by: Muralidhara M K Signed-off-by: Naveen Krishna Chatradhi [Rebased/reworked patch and reworded commit message] Signed-off-by: Yazen Ghannam --- drivers/edac/amd64_edac.c | 24 ++++++++++++++---------- drivers/edac/amd64_edac.h | 1 + 2 files changed, 15 insertions(+), 10 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 0bc9a3846773..b99eaa73131e 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -3697,7 +3697,17 @@ static bool umc_ecc_enabled(struct amd64_pvt *pvt) } static inline void -f17h_determine_edac_ctl_cap(struct mem_ctl_info *mci, struct amd64_pvt *pvt) +dct_determine_edac_ctl_cap(struct mem_ctl_info *mci, struct amd64_pvt *pvt) +{ + if (pvt->nbcap & NBCAP_SECDED) + mci->edac_ctl_cap |= EDAC_FLAG_SECDED; + + if (pvt->nbcap & NBCAP_CHIPKILL) + mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED; +} + +static inline void +umc_determine_edac_ctl_cap(struct mem_ctl_info *mci, struct amd64_pvt *pvt) { u8 i, ecc_en = 1, cpk_en = 1, dev_x4 = 1, dev_x16 = 1; @@ -3734,15 +3744,7 @@ static void setup_mci_misc_attrs(struct mem_ctl_info *mci) mci->mtype_cap = MEM_FLAG_DDR2 | MEM_FLAG_RDDR2; mci->edac_ctl_cap = EDAC_FLAG_NONE; - if (pvt->umc) { - f17h_determine_edac_ctl_cap(mci, pvt); - } else { - if (pvt->nbcap & NBCAP_SECDED) - mci->edac_ctl_cap |= EDAC_FLAG_SECDED; - - if (pvt->nbcap & NBCAP_CHIPKILL) - mci->edac_ctl_cap |= EDAC_FLAG_S4ECD4ED; - } + pvt->ops->determine_edac_ctl_cap(mci, pvt); mci->edac_cap = pvt->ops->determine_edac_cap(pvt); mci->mod_name = EDAC_MOD_STR; @@ -3765,6 +3767,7 @@ static struct low_ops umc_ops = { .read_mc_regs = umc_read_mc_regs, .ecc_enabled = umc_ecc_enabled, .determine_edac_cap = umc_determine_edac_cap, + .determine_edac_ctl_cap = umc_determine_edac_ctl_cap, }; /* Use Family 16h versions for defaults and adjust as needed below. */ @@ -3779,6 +3782,7 @@ static struct low_ops dct_ops = { .read_mc_regs = dct_read_mc_regs, .ecc_enabled = dct_ecc_enabled, .determine_edac_cap = dct_determine_edac_cap, + .determine_edac_ctl_cap = dct_determine_edac_ctl_cap, }; static int per_family_init(struct amd64_pvt *pvt) diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index bfe48492a0ba..15521adec9b5 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -475,6 +475,7 @@ struct low_ops { void (*read_mc_regs)(struct amd64_pvt *pvt); bool (*ecc_enabled)(struct amd64_pvt *pvt); unsigned long (*determine_edac_cap)(struct amd64_pvt *pvt); + void (*determine_edac_ctl_cap)(struct mem_ctl_info *mci, struct amd64_pvt *pvt); }; int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,