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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 May 2022 14:55:58.6315 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3fef4685-f6e9-4721-0c40-08da31cc0714 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT009.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4163 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Muralidhara M K GPU Nodes will use a different method to enumerate the chip select (struct dimm_info) values. A function pointer should be used rather than introduce another branching condition. Prepare for this by adding init_csrows() to pvt->ops and set it as needed based on currently supported systems. Use a "umc" prefix for modern systems, since these use Unified Memory Controllers (UMCs). Use a "dct" prefix for newly-defined legacy functions, since these systems use DRAM Controllers (DCTs). Signed-off-by: Muralidhara M K Signed-off-by: Naveen Krishna Chatradhi [Rebased/reworked patch and reworded commit message] Signed-off-by: Yazen Ghannam --- drivers/edac/amd64_edac.c | 11 +++++------ drivers/edac/amd64_edac.h | 1 + 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index f1346416e64d..5beeeb2fd6a8 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -3357,7 +3357,7 @@ static u32 get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr_orig) return nr_pages; } -static int init_csrows_df(struct mem_ctl_info *mci) +static int umc_init_csrows(struct mem_ctl_info *mci) { struct amd64_pvt *pvt = mci->pvt_info; enum edac_type edac_mode = EDAC_NONE; @@ -3405,7 +3405,7 @@ static int init_csrows_df(struct mem_ctl_info *mci) * Initialize the array of csrow attribute instances, based on the values * from pci config hardware registers. */ -static int init_csrows(struct mem_ctl_info *mci) +static int dct_init_csrows(struct mem_ctl_info *mci) { struct amd64_pvt *pvt = mci->pvt_info; enum edac_type edac_mode = EDAC_NONE; @@ -3415,9 +3415,6 @@ static int init_csrows(struct mem_ctl_info *mci) int nr_pages = 0; u32 val; - if (pvt->umc) - return init_csrows_df(mci); - amd64_read_pci_cfg(pvt->F3, NBCFG, &val); pvt->nbcfg = val; @@ -3768,6 +3765,7 @@ static struct low_ops umc_ops = { .ecc_enabled = umc_ecc_enabled, .determine_edac_cap = umc_determine_edac_cap, .determine_edac_ctl_cap = umc_determine_edac_ctl_cap, + .init_csrows = umc_init_csrows, .setup_mci_misc_attrs = setup_mci_misc_attrs, }; @@ -3784,6 +3782,7 @@ static struct low_ops dct_ops = { .ecc_enabled = dct_ecc_enabled, .determine_edac_cap = dct_determine_edac_cap, .determine_edac_ctl_cap = dct_determine_edac_ctl_cap, + .init_csrows = dct_init_csrows, .setup_mci_misc_attrs = setup_mci_misc_attrs, }; @@ -4005,7 +4004,7 @@ static int init_one_instance(struct amd64_pvt *pvt) pvt->ops->setup_mci_misc_attrs(mci); - if (init_csrows(mci)) + if (pvt->ops->init_csrows(mci)) mci->edac_cap = EDAC_FLAG_NONE; ret = -ENODEV; diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index 93de7dea516a..1b879c3cfb36 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -477,6 +477,7 @@ struct low_ops { unsigned long (*determine_edac_cap)(struct amd64_pvt *pvt); void (*determine_edac_ctl_cap)(struct mem_ctl_info *mci, struct amd64_pvt *pvt); void (*setup_mci_misc_attrs)(struct mem_ctl_info *mci); + int (*init_csrows)(struct mem_ctl_info *mci); }; int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,