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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 May 2022 14:55:58.9896 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1773b72f-abe8-4fe4-b29c-08da31cc074a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT012.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6276 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Muralidhara M K GPU Nodes will print out different information and registers compared to existing systems. A function pointer should be used rather than introduce another branching condition. Prepare for this by adding dump_misc_regs() to pvt->ops and set it as needed based on currently supported systems. Use a "umc" prefix for modern systems, since these use Unified Memory Controllers (UMCs). Use a "dct" prefix for newly-defined legacy functions, since these systems use DRAM Controllers (DCTs). Signed-off-by: Muralidhara M K Signed-off-by: Naveen Krishna Chatradhi [Rebased/reworked patch and reworded commit message] Signed-off-by: Yazen Ghannam --- drivers/edac/amd64_edac.c | 21 ++++++--------------- drivers/edac/amd64_edac.h | 1 + 2 files changed, 7 insertions(+), 15 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 5beeeb2fd6a8..b4c9d224f564 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1394,7 +1394,7 @@ static void debug_display_dimm_sizes_df(struct amd64_pvt *pvt, u8 ctrl) } } -static void __dump_misc_regs_df(struct amd64_pvt *pvt) +static void umc_dump_misc_regs(struct amd64_pvt *pvt) { struct amd64_umc *umc; u32 i, tmp, umc_base; @@ -1437,8 +1437,7 @@ static void __dump_misc_regs_df(struct amd64_pvt *pvt) } } -/* Display and decode various NB registers for debug purposes. */ -static void __dump_misc_regs(struct amd64_pvt *pvt) +static void dct_dump_misc_regs(struct amd64_pvt *pvt) { edac_dbg(1, "F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap); @@ -1473,17 +1472,6 @@ static void __dump_misc_regs(struct amd64_pvt *pvt) edac_dbg(1, " DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no"); } -/* Display and decode various NB registers for debug purposes. */ -static void dump_misc_regs(struct amd64_pvt *pvt) -{ - if (pvt->umc) - __dump_misc_regs_df(pvt); - else - __dump_misc_regs(pvt); - - amd64_info("using x%u syndromes.\n", pvt->ecc_sym_sz); -} - /* * See BKDG, F2x[1,0][5C:40], F2[1,0][6C:60] */ @@ -3766,6 +3754,7 @@ static struct low_ops umc_ops = { .determine_edac_cap = umc_determine_edac_cap, .determine_edac_ctl_cap = umc_determine_edac_ctl_cap, .init_csrows = umc_init_csrows, + .dump_misc_regs = umc_dump_misc_regs, .setup_mci_misc_attrs = setup_mci_misc_attrs, }; @@ -3783,6 +3772,7 @@ static struct low_ops dct_ops = { .determine_edac_cap = dct_determine_edac_cap, .determine_edac_ctl_cap = dct_determine_edac_ctl_cap, .init_csrows = dct_init_csrows, + .dump_misc_regs = dct_dump_misc_regs, .setup_mci_misc_attrs = setup_mci_misc_attrs, }; @@ -4093,7 +4083,8 @@ static int probe_one_instance(unsigned int nid) amd64_info("%s detected (node %d).\n", pvt->ctl_name, pvt->mc_node_id); - dump_misc_regs(pvt); + /* Display and decode various registers for debug purposes. */ + pvt->ops->dump_misc_regs(pvt); return ret; diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index 1b879c3cfb36..4e7467c285b9 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -478,6 +478,7 @@ struct low_ops { void (*determine_edac_ctl_cap)(struct mem_ctl_info *mci, struct amd64_pvt *pvt); void (*setup_mci_misc_attrs)(struct mem_ctl_info *mci); int (*init_csrows)(struct mem_ctl_info *mci); + void (*dump_misc_regs)(struct amd64_pvt *pvt); }; int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,