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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 May 2022 14:55:59.3189 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e0e1233f-5005-428d-8f89-08da31cc077a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT009.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5082 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Muralidhara M K GPU Nodes will use a different method to determine the chip select mode used on a controller. A function pointer should be used rather than introduce another branching condition. Prepare for this by adding get_cs_mode() to pvt->ops and set it as needed based on currently supported systems. Use a "umc" prefix for modern systems, since these use Unified Memory Controllers (UMCs). Use a "dct" prefix for newly-defined legacy functions, since these systems use DRAM Controllers (DCTs). Signed-off-by: Muralidhara M K Signed-off-by: Naveen Krishna Chatradhi [Rebased/reworked patch and reworded commit message] Signed-off-by: Yazen Ghannam --- drivers/edac/amd64_edac.c | 21 ++++++++++++--------- drivers/edac/amd64_edac.h | 1 + 2 files changed, 13 insertions(+), 9 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index b4c9d224f564..248d1082736e 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1341,7 +1341,14 @@ static void debug_dump_dramcfg_low(struct amd64_pvt *pvt, u32 dclr, int chan) #define CS_EVEN (CS_EVEN_PRIMARY | CS_EVEN_SECONDARY) #define CS_ODD (CS_ODD_PRIMARY | CS_ODD_SECONDARY) -static int f17_get_cs_mode(int dimm, u8 ctrl, struct amd64_pvt *pvt) +static int dct_get_cs_mode(int dimm, u8 ctrl, struct amd64_pvt *pvt) +{ + u32 dbam = ctrl ? pvt->dbam1 : pvt->dbam0; + + return DBAM_DIMM(dimm, dbam); +} + +static int umc_get_cs_mode(int dimm, u8 ctrl, struct amd64_pvt *pvt) { u8 base, count = 0; int cs_mode = 0; @@ -1383,7 +1390,7 @@ static void debug_display_dimm_sizes_df(struct amd64_pvt *pvt, u8 ctrl) cs0 = dimm * 2; cs1 = dimm * 2 + 1; - cs_mode = f17_get_cs_mode(dimm, ctrl, pvt); + cs_mode = umc_get_cs_mode(dimm, ctrl, pvt); size0 = pvt->ops->dbam_to_cs(pvt, ctrl, cs_mode, cs0); size1 = pvt->ops->dbam_to_cs(pvt, ctrl, cs_mode, cs1); @@ -3324,16 +3331,10 @@ static void dct_read_mc_regs(struct amd64_pvt *pvt) */ static u32 get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr_orig) { - u32 dbam = dct ? pvt->dbam1 : pvt->dbam0; int csrow_nr = csrow_nr_orig; u32 cs_mode, nr_pages; - if (!pvt->umc) { - csrow_nr >>= 1; - cs_mode = DBAM_DIMM(csrow_nr, dbam); - } else { - cs_mode = f17_get_cs_mode(csrow_nr >> 1, dct, pvt); - } + cs_mode = pvt->ops->get_cs_mode(csrow_nr >> 1, dct, pvt); nr_pages = pvt->ops->dbam_to_cs(pvt, dct, cs_mode, csrow_nr); nr_pages <<= 20 - PAGE_SHIFT; @@ -3755,6 +3756,7 @@ static struct low_ops umc_ops = { .determine_edac_ctl_cap = umc_determine_edac_ctl_cap, .init_csrows = umc_init_csrows, .dump_misc_regs = umc_dump_misc_regs, + .get_cs_mode = umc_get_cs_mode, .setup_mci_misc_attrs = setup_mci_misc_attrs, }; @@ -3773,6 +3775,7 @@ static struct low_ops dct_ops = { .determine_edac_ctl_cap = dct_determine_edac_ctl_cap, .init_csrows = dct_init_csrows, .dump_misc_regs = dct_dump_misc_regs, + .get_cs_mode = dct_get_cs_mode, .setup_mci_misc_attrs = setup_mci_misc_attrs, }; diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index 4e7467c285b9..1f64c08ae0ce 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -479,6 +479,7 @@ struct low_ops { void (*setup_mci_misc_attrs)(struct mem_ctl_info *mci); int (*init_csrows)(struct mem_ctl_info *mci); void (*dump_misc_regs)(struct amd64_pvt *pvt); + int (*get_cs_mode)(int dimm, u8 ctrl, struct amd64_pvt *pvt); }; int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,