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Mon, 9 May 2022 14:55:56 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT009.mail.protection.outlook.com (10.13.175.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5227.15 via Frontend Transport; Mon, 9 May 2022 14:55:55 +0000 Received: from yaz-ethanolx.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Mon, 9 May 2022 09:55:48 -0500 From: Yazen Ghannam To: , CC: , , , , Yazen Ghannam Subject: [PATCH 07/18] EDAC/amd64: Add read_base_mask() into pvt->ops Date: Mon, 9 May 2022 14:55:23 +0000 Message-ID: <20220509145534.44912-8-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509145534.44912-1-yazen.ghannam@amd.com> References: <20220509145534.44912-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: c7528b3a-4d69-4d4b-c5d4-08da31cc055f X-MS-TrafficTypeDiagnostic: BL0PR12MB4691:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 May 2022 14:55:55.7879 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c7528b3a-4d69-4d4b-c5d4-08da31cc055f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT009.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR12MB4691 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Muralidhara M K GPU Nodes will need to set the read the Base and Mask values differently than existing systems. A function pointer should be used rather than introduce another branching condition. Prepare for this by adding read_base_mask() to pvt->ops and set it as needed based on currently supported systems. Use a "umc" prefix for modern systems, since these use Unified Memory Controllers (UMCs). Use a "dct" prefix for newly-defined legacy functions, since these systems use DRAM Controllers (DCTs). Signed-off-by: Muralidhara M K Signed-off-by: Naveen Krishna Chatradhi [Rebased/reworked patch and reworded commit message] Signed-off-by: Yazen Ghannam --- drivers/edac/amd64_edac.c | 11 +++++------ drivers/edac/amd64_edac.h | 1 + 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index f8cd89278753..6e26bbb73f81 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1507,7 +1507,7 @@ static void umc_prep_chip_selects(struct amd64_pvt *pvt) } } -static void read_umc_base_mask(struct amd64_pvt *pvt) +static void umc_read_base_mask(struct amd64_pvt *pvt) { u32 umc_base_reg, umc_base_reg_sec; u32 umc_mask_reg, umc_mask_reg_sec; @@ -1561,13 +1561,10 @@ static void read_umc_base_mask(struct amd64_pvt *pvt) /* * Function 2 Offset F10_DCSB0; read in the DCS Base and DCS Mask registers */ -static void read_dct_base_mask(struct amd64_pvt *pvt) +static void dct_read_base_mask(struct amd64_pvt *pvt) { int cs; - if (pvt->umc) - return read_umc_base_mask(pvt); - for_each_chip_select(cs, 0, pvt) { int reg0 = DCSB0 + (cs * 4); int reg1 = DCSB1 + (cs * 4); @@ -3303,7 +3300,7 @@ static void read_mc_regs(struct amd64_pvt *pvt) skip: pvt->ops->prep_chip_selects(pvt); - read_dct_base_mask(pvt); + pvt->ops->read_base_mask(pvt); determine_memory_type(pvt); @@ -3765,6 +3762,7 @@ static struct low_ops umc_ops = { .early_channel_count = umc_early_channel_count, .dbam_to_cs = umc_addr_mask_to_cs_size, .prep_chip_selects = umc_prep_chip_selects, + .read_base_mask = umc_read_base_mask, }; /* Use Family 16h versions for defaults and adjust as needed below. */ @@ -3773,6 +3771,7 @@ static struct low_ops dct_ops = { .map_sysaddr_to_csrow = f1x_map_sysaddr_to_csrow, .dbam_to_cs = f16_dbam_to_chip_select, .prep_chip_selects = dct_prep_chip_selects, + .read_base_mask = dct_read_base_mask, }; static int per_family_init(struct amd64_pvt *pvt) diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index 0a7738df396f..c81cc7f5fc96 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -469,6 +469,7 @@ struct low_ops { int (*dbam_to_cs)(struct amd64_pvt *pvt, u8 dct, unsigned int cs_mode, int cs_mask_nr); void (*prep_chip_selects)(struct amd64_pvt *pvt); + void (*read_base_mask)(struct amd64_pvt *pvt); }; int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,