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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 May 2022 14:55:55.8431 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 84e6ef3e-585e-4a3f-94b5-08da31cc056a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT064.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4296 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Muralidhara M K GPU Nodes will need to set the EDAC memory type differently than existing systems. A function pointer should be used rather than introduce another branching condition. Prepare for this by adding determine_memory_type() to pvt->ops and set it as needed based on currently supported systems. Use a "umc" prefix for modern systems, since these use Unified Memory Controllers (UMCs). Use a "dct" prefix for newly-defined legacy functions, since these systems use DRAM Controllers (DCTs). Signed-off-by: Muralidhara M K Signed-off-by: Naveen Krishna Chatradhi [Rebased/reworked patch and reworded commit message] Signed-off-by: Yazen Ghannam --- drivers/edac/amd64_edac.c | 16 +++++++--------- drivers/edac/amd64_edac.h | 1 + 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 6e26bbb73f81..a767d8a6bfe8 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1604,7 +1604,7 @@ static void dct_read_base_mask(struct amd64_pvt *pvt) } } -static void determine_memory_type_df(struct amd64_pvt *pvt) +static void umc_determine_memory_type(struct amd64_pvt *pvt) { struct amd64_umc *umc; u32 i; @@ -1641,13 +1641,10 @@ static void determine_memory_type_df(struct amd64_pvt *pvt) } } -static void determine_memory_type(struct amd64_pvt *pvt) +static void dct_determine_memory_type(struct amd64_pvt *pvt) { u32 dram_ctrl, dcsm; - if (pvt->umc) - return determine_memory_type_df(pvt); - switch (pvt->fam) { case 0xf: if (pvt->ext_model >= K8_REV_F) @@ -1697,6 +1694,8 @@ static void determine_memory_type(struct amd64_pvt *pvt) WARN(1, KERN_ERR "%s: Family??? 0x%x\n", __func__, pvt->fam); pvt->dram_type = MEM_EMPTY; } + + edac_dbg(1, " DIMM type: %s\n", edac_mem_types[pvt->dram_type]); return; ddr3: @@ -3302,10 +3301,7 @@ static void read_mc_regs(struct amd64_pvt *pvt) pvt->ops->read_base_mask(pvt); - determine_memory_type(pvt); - - if (!pvt->umc) - edac_dbg(1, " DIMM type: %s\n", edac_mem_types[pvt->dram_type]); + pvt->ops->determine_memory_type(pvt); determine_ecc_sym_sz(pvt); } @@ -3763,6 +3759,7 @@ static struct low_ops umc_ops = { .dbam_to_cs = umc_addr_mask_to_cs_size, .prep_chip_selects = umc_prep_chip_selects, .read_base_mask = umc_read_base_mask, + .determine_memory_type = umc_determine_memory_type, }; /* Use Family 16h versions for defaults and adjust as needed below. */ @@ -3772,6 +3769,7 @@ static struct low_ops dct_ops = { .dbam_to_cs = f16_dbam_to_chip_select, .prep_chip_selects = dct_prep_chip_selects, .read_base_mask = dct_read_base_mask, + .determine_memory_type = dct_determine_memory_type, }; static int per_family_init(struct amd64_pvt *pvt) diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h index c81cc7f5fc96..da3db0f4f59b 100644 --- a/drivers/edac/amd64_edac.h +++ b/drivers/edac/amd64_edac.h @@ -470,6 +470,7 @@ struct low_ops { unsigned int cs_mode, int cs_mask_nr); void (*prep_chip_selects)(struct amd64_pvt *pvt); void (*read_base_mask)(struct amd64_pvt *pvt); + void (*determine_memory_type)(struct amd64_pvt *pvt); }; int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,