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Fri, 26 Aug 2022 23:39:56 +0000 Received: from SJ0PR10MB4429.namprd10.prod.outlook.com ([fe80::14cf:1363:8f81:9c81]) by SJ0PR10MB4429.namprd10.prod.outlook.com ([fe80::14cf:1363:8f81:9c81%4]) with mapi id 15.20.5566.016; Fri, 26 Aug 2022 23:39:55 +0000 From: Jane Chu To: tony.luck@intel.com, bp@alien8.de, tglx@linutronix.de, mingo@redhat.com, dave.hansen@linux.intel.com, x86@kernel.org, linux-edac@vger.kernel.org, dan.j.williams@intel.com, linux-kernel@vger.kernel.org, hch@lst.de, nvdimm@lists.linux.dev Subject: [PATCH v8] x86/mce: retrieve poison range from hardware Date: Fri, 26 Aug 2022 17:38:51 -0600 Message-Id: <20220826233851.1319100-1-jane.chu@oracle.com> X-Mailer: git-send-email 2.18.4 X-ClientProxiedBy: DM6PR11CA0029.namprd11.prod.outlook.com (2603:10b6:5:190::42) To SJ0PR10MB4429.namprd10.prod.outlook.com (2603:10b6:a03:2d1::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: aeb9ba84-9de7-42b9-7d34-08da87bc47fa X-MS-TrafficTypeDiagnostic: CY5PR10MB5915:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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The error information includes data about blast radius, i.e. how many cachelines did the hardware determine are impacted. A recent change, commit 7917f9cdb503 ("acpi/nfit: rely on mce->misc to determine poison granularity"), updated nfit_handle_mce() to stop hard coding the blast radius value of 1 cacheline, and instead rely on the blast radius reported in 'struct mce' which can be up to 4K (64 cachelines). It turns out that apei_mce_report_mem_error() had a similar problem in that it hard coded a blast radius of 4K rather than reading the blast radius from the error information. Fix apei_mce_report_mem_error() to convey the proper poison granularity. Link: https://lore.kernel.org/r/7ed50fd8-521e-cade-77b1-738b8bfb8502@oracle.com Reviewed-by: Dan Williams Reviewed-by: Ingo Molnar Signed-off-by: Jane Chu --- arch/x86/kernel/cpu/mce/apei.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/mce/apei.c b/arch/x86/kernel/cpu/mce/apei.c index 717192915f28..8ed341714686 100644 --- a/arch/x86/kernel/cpu/mce/apei.c +++ b/arch/x86/kernel/cpu/mce/apei.c @@ -29,15 +29,26 @@ void apei_mce_report_mem_error(int severity, struct cper_sec_mem_err *mem_err) { struct mce m; + int lsb; if (!(mem_err->validation_bits & CPER_MEM_VALID_PA)) return; + /* + * Even if the ->validation_bits are set for address mask, + * to be extra safe, check and reject an error radius '0', + * and fall back to the default page size. + */ + if (mem_err->validation_bits & CPER_MEM_VALID_PA_MASK) + lsb = find_first_bit((void *)&mem_err->physical_addr_mask, PAGE_SHIFT); + else + lsb = PAGE_SHIFT; + mce_setup(&m); m.bank = -1; /* Fake a memory read error with unknown channel */ m.status = MCI_STATUS_VAL | MCI_STATUS_EN | MCI_STATUS_ADDRV | MCI_STATUS_MISCV | 0x9f; - m.misc = (MCI_MISC_ADDR_PHYS << 6) | PAGE_SHIFT; + m.misc = (MCI_MISC_ADDR_PHYS << 6) | lsb; if (severity >= GHES_SEV_RECOVERABLE) m.status |= MCI_STATUS_UC;