| Message ID | 20220910194237.10142-6-Sergey.Semin@baikalelectronics.ru (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | EDAC/mc/synopsys: Various fixes and cleanups | expand |
[AMD Official Use Only - General] > -----Original Message----- > From: Serge Semin <Sergey.Semin@baikalelectronics.ru> > Sent: Sunday, September 11, 2022 1:12 AM > To: Rob Herring <robh+dt@kernel.org>; Krzysztof Kozlowski > <krzysztof.kozlowski+dt@linaro.org>; Michal Simek > <michal.simek@xilinx.com>; Borislav Petkov <bp@alien8.de>; Mauro > Carvalho Chehab <mchehab@kernel.org>; Tony Luck > <tony.luck@intel.com>; James Morse <james.morse@arm.com>; Robert > Richter <rric@kernel.org>; Shubhrajyoti Datta > <shubhrajyoti.datta@xilinx.com> > Cc: Serge Semin <Sergey.Semin@baikalelectronics.ru>; Serge Semin > <fancer.lancer@gmail.com>; Alexey Malahov > <Alexey.Malahov@baikalelectronics.ru>; Michail Ivanov > <Michail.Ivanov@baikalelectronics.ru>; Pavel Parkhomenko > <Pavel.Parkhomenko@baikalelectronics.ru>; Punnaiah Choudary Kalluri > <punnaiah.choudary.kalluri@xilinx.com>; Manish Narani > <manish.narani@xilinx.com>; Dinh Nguyen <dinguyen@kernel.org>; Rob > Herring <robh@kernel.org>; Krzysztof Kozlowski > <krzysztof.kozlowski@linaro.org>; devicetree@vger.kernel.org; linux-arm- > kernel@lists.infradead.org; linux-edac@vger.kernel.org; linux- > kernel@vger.kernel.org; Borislav Petkov <bp@suse.de> > Subject: [PATCH v2 05/19] EDAC/synopsys: Fix reading errors count before > ECC status > > CAUTION: This message has originated from an External Source. Please use > proper judgment and caution when opening attachments, clicking links, or > responding to this email. > > > Aside with fixing the errors count CSR usage the commit e2932d1f6f05 > ("EDAC/synopsys: Read the error count from the correct register") all of the > sudden has also changed the order of the errors status check procedure. So > now the errors handler method first reads the number of CE and UE and only > then makes sure that any of these errors have actually happened. It doesn't > make much sense. Let's fix that by getting back the procedures order: first > check the ECC status, then read the number of errors. > > Fixes: e2932d1f6f05 ("EDAC/synopsys: Read the error count from the correct > register") > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Reviewed-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> > --- > drivers/edac/synopsys_edac.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c > index da1d90a87778..558d3b3e6864 100644 > --- a/drivers/edac/synopsys_edac.c > +++ b/drivers/edac/synopsys_edac.c > @@ -423,18 +423,18 @@ static int zynqmp_get_error_info(struct > synps_edac_priv *priv) > base = priv->baseaddr; > p = &priv->stat; > > - regval = readl(base + ECC_ERRCNT_OFST); > - p->ce_cnt = regval & ECC_ERRCNT_CECNT_MASK; > - p->ue_cnt = (regval & ECC_ERRCNT_UECNT_MASK) >> > ECC_ERRCNT_UECNT_SHIFT; > - if (!p->ce_cnt) > - goto ue_err; > - > regval = readl(base + ECC_STAT_OFST); > if (!regval) > return 1; > > p->ceinfo.bitpos = (regval & ECC_STAT_BITNUM_MASK); > > + regval = readl(base + ECC_ERRCNT_OFST); > + p->ce_cnt = regval & ECC_ERRCNT_CECNT_MASK; > + p->ue_cnt = (regval & ECC_ERRCNT_UECNT_MASK) >> > ECC_ERRCNT_UECNT_SHIFT; > + if (!p->ce_cnt) > + goto ue_err; > + > regval = readl(base + ECC_CEADDR0_OFST); > p->ceinfo.row = (regval & ECC_CEADDR0_RW_MASK); > regval = readl(base + ECC_CEADDR1_OFST); > -- > 2.37.2
diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index da1d90a87778..558d3b3e6864 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -423,18 +423,18 @@ static int zynqmp_get_error_info(struct synps_edac_priv *priv) base = priv->baseaddr; p = &priv->stat; - regval = readl(base + ECC_ERRCNT_OFST); - p->ce_cnt = regval & ECC_ERRCNT_CECNT_MASK; - p->ue_cnt = (regval & ECC_ERRCNT_UECNT_MASK) >> ECC_ERRCNT_UECNT_SHIFT; - if (!p->ce_cnt) - goto ue_err; - regval = readl(base + ECC_STAT_OFST); if (!regval) return 1; p->ceinfo.bitpos = (regval & ECC_STAT_BITNUM_MASK); + regval = readl(base + ECC_ERRCNT_OFST); + p->ce_cnt = regval & ECC_ERRCNT_CECNT_MASK; + p->ue_cnt = (regval & ECC_ERRCNT_UECNT_MASK) >> ECC_ERRCNT_UECNT_SHIFT; + if (!p->ce_cnt) + goto ue_err; + regval = readl(base + ECC_CEADDR0_OFST); p->ceinfo.row = (regval & ECC_CEADDR0_RW_MASK); regval = readl(base + ECC_CEADDR1_OFST);
Aside with fixing the errors count CSR usage the commit e2932d1f6f05 ("EDAC/synopsys: Read the error count from the correct register") all of the sudden has also changed the order of the errors status check procedure. So now the errors handler method first reads the number of CE and UE and only then makes sure that any of these errors have actually happened. It doesn't make much sense. Let's fix that by getting back the procedures order: first check the ECC status, then read the number of errors. Fixes: e2932d1f6f05 ("EDAC/synopsys: Read the error count from the correct register") Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> --- drivers/edac/synopsys_edac.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)