| Message ID | 20221018153630.14664-1-yazen.ghannam@amd.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | EDAC/mc_sysfs: Increase legacy channel support to 12 | expand |
On Tue, Oct 18, 2022 at 10:36:30AM -0500, Yazen Ghannam wrote: > Newer AMD systems, such as Genoa, can support up to 12 channels per EDAC > "mc" device. These are detected by the device's EDAC module, and the > current EDAC interface is properly enumerated. However, the legacy EDAC > sysfs interface provides device attributes only for channels 0 to 7. > Therefore, channels 8 to 11 will not be visible in the legacy interface. > This was overlooked in the initial support for AMD Genoa. > > Add additional device attributes so that up to 12 channels are visible > in the legacy EDAC sysfs interface. > > Ignore checkpatch warnings about "Symbolic permissions" to maintain > coding style. > > Fixes: e2be5955a886 ("EDAC/amd64: Add support for AMD Family 19h Models 10h-1Fh and A0h-AFh") > Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> > Cc: <stable@vger.kernel.org> > --- > drivers/edac/edac_mc_sysfs.c | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) Applied, thanks.
On Mon, Oct 31, 2022 at 11:26:44AM +0100, Borislav Petkov wrote: > On Tue, Oct 18, 2022 at 10:36:30AM -0500, Yazen Ghannam wrote: > > Newer AMD systems, such as Genoa, can support up to 12 channels per EDAC > > "mc" device. These are detected by the device's EDAC module, and the > > current EDAC interface is properly enumerated. However, the legacy EDAC > > sysfs interface provides device attributes only for channels 0 to 7. > > Therefore, channels 8 to 11 will not be visible in the legacy interface. > > This was overlooked in the initial support for AMD Genoa. > > > > Add additional device attributes so that up to 12 channels are visible > > in the legacy EDAC sysfs interface. > > > > Ignore checkpatch warnings about "Symbolic permissions" to maintain > > coding style. > > > > Fixes: e2be5955a886 ("EDAC/amd64: Add support for AMD Family 19h Models 10h-1Fh and A0h-AFh") > > Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> > > Cc: <stable@vger.kernel.org> > > --- > > drivers/edac/edac_mc_sysfs.c | 24 ++++++++++++++++++++++++ > > 1 file changed, 24 insertions(+) > > Applied, thanks. > Thank you! -Yazen
diff --git a/drivers/edac/edac_mc_sysfs.c b/drivers/edac/edac_mc_sysfs.c index 0a638c97702a..15f63452a9be 100644 --- a/drivers/edac/edac_mc_sysfs.c +++ b/drivers/edac/edac_mc_sysfs.c @@ -298,6 +298,14 @@ DEVICE_CHANNEL(ch6_dimm_label, S_IRUGO | S_IWUSR, channel_dimm_label_show, channel_dimm_label_store, 6); DEVICE_CHANNEL(ch7_dimm_label, S_IRUGO | S_IWUSR, channel_dimm_label_show, channel_dimm_label_store, 7); +DEVICE_CHANNEL(ch8_dimm_label, S_IRUGO | S_IWUSR, + channel_dimm_label_show, channel_dimm_label_store, 8); +DEVICE_CHANNEL(ch9_dimm_label, S_IRUGO | S_IWUSR, + channel_dimm_label_show, channel_dimm_label_store, 9); +DEVICE_CHANNEL(ch10_dimm_label, S_IRUGO | S_IWUSR, + channel_dimm_label_show, channel_dimm_label_store, 10); +DEVICE_CHANNEL(ch11_dimm_label, S_IRUGO | S_IWUSR, + channel_dimm_label_show, channel_dimm_label_store, 11); /* Total possible dynamic DIMM Label attribute file table */ static struct attribute *dynamic_csrow_dimm_attr[] = { @@ -309,6 +317,10 @@ static struct attribute *dynamic_csrow_dimm_attr[] = { &dev_attr_legacy_ch5_dimm_label.attr.attr, &dev_attr_legacy_ch6_dimm_label.attr.attr, &dev_attr_legacy_ch7_dimm_label.attr.attr, + &dev_attr_legacy_ch8_dimm_label.attr.attr, + &dev_attr_legacy_ch9_dimm_label.attr.attr, + &dev_attr_legacy_ch10_dimm_label.attr.attr, + &dev_attr_legacy_ch11_dimm_label.attr.attr, NULL }; @@ -329,6 +341,14 @@ DEVICE_CHANNEL(ch6_ce_count, S_IRUGO, channel_ce_count_show, NULL, 6); DEVICE_CHANNEL(ch7_ce_count, S_IRUGO, channel_ce_count_show, NULL, 7); +DEVICE_CHANNEL(ch8_ce_count, S_IRUGO, + channel_ce_count_show, NULL, 8); +DEVICE_CHANNEL(ch9_ce_count, S_IRUGO, + channel_ce_count_show, NULL, 9); +DEVICE_CHANNEL(ch10_ce_count, S_IRUGO, + channel_ce_count_show, NULL, 10); +DEVICE_CHANNEL(ch11_ce_count, S_IRUGO, + channel_ce_count_show, NULL, 11); /* Total possible dynamic ce_count attribute file table */ static struct attribute *dynamic_csrow_ce_count_attr[] = { @@ -340,6 +360,10 @@ static struct attribute *dynamic_csrow_ce_count_attr[] = { &dev_attr_legacy_ch5_ce_count.attr.attr, &dev_attr_legacy_ch6_ce_count.attr.attr, &dev_attr_legacy_ch7_ce_count.attr.attr, + &dev_attr_legacy_ch8_ce_count.attr.attr, + &dev_attr_legacy_ch9_ce_count.attr.attr, + &dev_attr_legacy_ch10_ce_count.attr.attr, + &dev_attr_legacy_ch11_ce_count.attr.attr, NULL };
Newer AMD systems, such as Genoa, can support up to 12 channels per EDAC "mc" device. These are detected by the device's EDAC module, and the current EDAC interface is properly enumerated. However, the legacy EDAC sysfs interface provides device attributes only for channels 0 to 7. Therefore, channels 8 to 11 will not be visible in the legacy interface. This was overlooked in the initial support for AMD Genoa. Add additional device attributes so that up to 12 channels are visible in the legacy EDAC sysfs interface. Ignore checkpatch warnings about "Symbolic permissions" to maintain coding style. Fixes: e2be5955a886 ("EDAC/amd64: Add support for AMD Family 19h Models 10h-1Fh and A0h-AFh") Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> Cc: <stable@vger.kernel.org> --- drivers/edac/edac_mc_sysfs.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)