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Wed, 2 Nov 2022 03:46:15 -0500 Received: from xhdshubhraj40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.31 via Frontend Transport; Wed, 2 Nov 2022 03:46:12 -0500 From: Shubhrajyoti Datta To: CC: , , , , , , , , , Subject: [PATCH 1/2] dt-bindings: edac: Add bindings for Xilinx Versal EDAC for DDRMC Date: Wed, 2 Nov 2022 14:16:07 +0530 Message-ID: <20221102084608.28894-2-shubhrajyoti.datta@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221102084608.28894-1-shubhrajyoti.datta@amd.com> References: <20221102084608.28894-1-shubhrajyoti.datta@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT003:EE_|DM6PR12MB4058:EE_ X-MS-Office365-Filtering-Correlation-Id: 1a9e3109-5c04-4e0e-0984-08dabcaeb50e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: gYDGQ1K4OKfr3xgtufZYdxogsxIYFB2MGvvf8fv5AQp3uD/hYzhdreP4/HtM0edG4jTWxznqYZHUXUW61J2rH9iOM+8vCvEbiLu7aKTebKCud4JBQxw+AR/B5ezyFj4NhJ0FzCJ4eOxrdG/zwT49+9wbOB1Ael80DY/dyn8TUJMmFwEsBKnOMyq5Uakdcj1otsMB2wwXOZobZz4rppwFnDTuhOs34N4B2UJNL8du61/2VYULP9JgUMLQDux39dMebRkouKBqnDNSS0AymByhB8LTu3bQGyydwHnDnq3PCmH/UgoKuAOXBzytGq1xf4Rzv/UrDUEUt7sro/T6XRLst5tZrZJu0LJxkvw9/qUcaGA/JJyFY4JDy6nZgCN1M4V3xdTwbi7OBs34p9dhllI9mzm2mhqQMQSw4m0hiFyVF0IDFkIobUqgFRPMKA8n90ApMRAkDs77oiNlkNlRFkVXTj5lxq6YbygrKINxnKY8+oa/wLFb0jFPaZpdOvQMrRgVUl0zK+rmdkqr/zWVcIvXuUqbK7Y0nhO7HGswv+HRoKn2xysrJTIMQ76odz1ho1SyfnmXHM5/A4/+Xb7YmFPjjkFRwwSEHdQWBF5fbbHs6Vl713pIu73Ik8sJLJmzvR9CdJtNX77jRRDX0ghXeo4qSJLRXUl6VQL9ngxUfm1B6gWzDkcvo4WpgCedzDOAnvpSXQH39o0G3psE0K72UcSKkzY5H/VgTVf8Oc2+/QucF/byhkBWAhmx8d3ai7+yHVw9YnAxOoHNnStdVPr3uKmVKLp0Mt290xB42IUH0bCUWicxCx7xy9/SYOVHE4nFc63MfLC8wuymfDkGgzURs8MypDQ5DORcTV4ddFuOYS6o7FOT9bt0PCmebm5n7Ps/MPQJ X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(396003)(346002)(39860400002)(376002)(136003)(451199015)(46966006)(36840700001)(40470700004)(2616005)(6666004)(82310400005)(44832011)(316002)(83380400001)(41300700001)(36860700001)(82740400003)(86362001)(26005)(966005)(81166007)(356005)(4326008)(8676002)(70586007)(70206006)(40460700003)(36756003)(54906003)(6916009)(1076003)(478600001)(336012)(40480700001)(5660300002)(186003)(8936002)(47076005)(426003)(2906002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Nov 2022 08:46:17.3336 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1a9e3109-5c04-4e0e-0984-08dabcaeb50e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT003.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4058 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org This patch adds device tree bindings for Xilinx Versal EDAC for DDR controller. Co-developed-by: Sai Krishna Potthuri Signed-off-by: Sai Krishna Potthuri Signed-off-by: Shubhrajyoti Datta --- .../xlnx,versal-ddrmc-edac.yaml | 57 +++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml b/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml new file mode 100644 index 000000000000..6717bc0f3be9 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-ddrmc-edac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Versal DDRMC (Integrated DDR Memory Controller) + +maintainers: + - Shubhrajyoti Datta + - Sai Krishna Potthuri + +description: + The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and LPDDR4/ + 4X memory interfaces. Versal DDR memory controller has an optional ECC support + which correct single bit ECC errors and detect double bit ECC errors. + +properties: + compatible: + const: xlnx,versal-ddrmc-edac + + reg: + items: + - description: DDR Memory Controller registers + - description: NOC registers corresponding to DDR Memory Controller + + reg-names: + items: + - const: ddrmc_base + - const: ddrmc_noc_base + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - interrupts + +additionalProperties: false + +examples: + - | + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + memory-controller@f6150000 { + compatible = "xlnx,versal-ddrmc-edac"; + reg = <0x0 0xf6150000 0x0 0x2000>, <0x0 0xf6070000 0x0 0x20000>; + reg-names = "ddrmc_base", "ddrmc_noc_base"; + interrupt-parent = <&gic>; + interrupts = ; + }; + };