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Mon, 16 Jan 2023 19:11:36 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT085.mail.protection.outlook.com (10.13.174.137) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6002.13 via Frontend Transport; Mon, 16 Jan 2023 19:11:36 +0000 Received: from onyx-7400host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 16 Jan 2023 13:11:35 -0600 From: Avadhut Naik To: , CC: , , , , Subject: [PATCH v1 2/3] x86/MCE/AMD: Add HWID Fixup for PCS_XGMI SMCA Date: Mon, 16 Jan 2023 19:11:01 +0000 Message-ID: <20230116191102.4226-3-avadnaik@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230116191102.4226-1-avadnaik@amd.com> References: <20230116191102.4226-1-avadnaik@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT085:EE_|DS7PR12MB8345:EE_ X-MS-Office365-Filtering-Correlation-Id: ae6a2550-cbcc-44df-5fd4-08daf7f57d41 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jan 2023 19:11:36.5112 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ae6a2550-cbcc-44df-5fd4-08daf7f57d41 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT085.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB8345 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org On AMD systems, during Scalable MCA (SMCA) initialization, the HWID and McaType tuple, read from MCA_IPID register of a SMCA bank type, is used by the kernel for populating the per-CPU smca_banks array. This very array is, in turn being utilized by the edac_mce_amd module for determining the SMCA bank type while decoding a machine check error. However, on some AMD CPUs, the HWID read from the MCA_IPID register for XGMI Controller SMCA bank type does not match the value expected by the kernel. Consequently, the smca_banks array is not populated for the bank type resulting in the machine check errors on the bank type not being decoded. As a solution, set the HWID, obtained from the MCA_IPID register, of the XGMI Controller SMCA bank type on affected CPUs, to the value expected by the kernel to ensure that the machine check errors on the bank type are correctly decoded. Signed-off-by: Avadhut Naik --- arch/x86/kernel/cpu/mce/amd.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 23c5072fbbb7..b0cce0ce056c 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -249,6 +249,30 @@ static void default_deferred_error_interrupt(void) } void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt; +/* + * Errata encountered on AMD CPUs for some SMCA bank types requires fixup + * of HWID, read from MCA_IPID register, for accurate SMCA error decoding. + */ +static inline void fixup_hwid(unsigned int *hwid_mcatype) +{ + struct cpuinfo_x86 *c = &boot_cpu_data; + + if (c->x86 == 0x19) { + switch (c->x86_model) { + /* + * Handle discrepancy in HWID of kernel and MCA_IPID register + * for XGMI Controller SMCA bank type + */ + case 0x30 ... 0x3F: + if (*hwid_mcatype == HWID_MCATYPE(0x80, 0x0)) + *hwid_mcatype = HWID_MCATYPE(0x50, 0x0); + break; + default: + break; + } + } +} + static void smca_set_misc_banks_map(unsigned int bank, unsigned int cpu) { u32 low, high; @@ -321,6 +345,8 @@ static void smca_configure(unsigned int bank, unsigned int cpu) hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID, (high & MCI_IPID_MCATYPE) >> 16); + fixup_hwid(&hwid_mcatype); + for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) { s_hwid = &smca_hwid_mcatypes[i];