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Fri, 27 Jan 2023 17:04:37 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT089.mail.protection.outlook.com (10.13.176.105) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6023.16 via Frontend Transport; Fri, 27 Jan 2023 17:04:37 +0000 Received: from yaz-ethanolx.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Fri, 27 Jan 2023 11:04:36 -0600 From: Yazen Ghannam To: , CC: , , , Yazen Ghannam Subject: [PATCH v2 15/22] EDAC/amd64: Split read_mc_regs() into dct/umc functions Date: Fri, 27 Jan 2023 17:04:12 +0000 Message-ID: <20230127170419.1824692-16-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230127170419.1824692-1-yazen.ghannam@amd.com> References: <20230127170419.1824692-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT089:EE_|IA1PR12MB8237:EE_ X-MS-Office365-Filtering-Correlation-Id: 0c0f837d-8b11-41a2-570b-08db00889256 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jan 2023 17:04:37.3428 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0c0f837d-8b11-41a2-570b-08db00889256 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT089.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8237 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org From: Muralidhara M K ...and call them from their respective hw_info_get() paths. ECC symbol size is not needed on UMC systems, so determine_ecc_sym_sz() is left out of the UMC path. Signed-off-by: Muralidhara M K Co-developed-by: Naveen Krishna Chatradhi Signed-off-by: Naveen Krishna Chatradhi [Rebased/reworked patch and reworded commit message] Co-developed-by: Yazen Ghannam Signed-off-by: Yazen Ghannam --- Link: https://lore.kernel.org/r/20220509145534.44912-11-yazen.ghannam@amd.com v1->v2: * Call functions directly instead of using pointers. drivers/edac/amd64_edac.c | 17 ++++------------- 1 file changed, 4 insertions(+), 13 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 0d0e563c99db..757d35fad2a6 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -3089,7 +3089,7 @@ static void determine_ecc_sym_sz(struct amd64_pvt *pvt) /* * Retrieve the hardware registers of the memory controller. */ -static void __read_mc_regs_df(struct amd64_pvt *pvt) +static void umc_read_mc_regs(struct amd64_pvt *pvt) { u8 nid = pvt->mc_node_id; struct amd64_umc *umc; @@ -3113,7 +3113,7 @@ static void __read_mc_regs_df(struct amd64_pvt *pvt) * Retrieve the hardware registers of the memory controller (this includes the * 'Address Map' and 'Misc' device regs) */ -static void read_mc_regs(struct amd64_pvt *pvt) +static void dct_read_mc_regs(struct amd64_pvt *pvt) { unsigned int range; u64 msr_val; @@ -3134,12 +3134,6 @@ static void read_mc_regs(struct amd64_pvt *pvt) edac_dbg(0, " TOP_MEM2 disabled\n"); } - if (pvt->umc) { - __read_mc_regs_df(pvt); - - goto skip; - } - amd64_read_pci_cfg(pvt->F3, NBCAP, &pvt->nbcap); read_dram_ctl_register(pvt); @@ -3180,9 +3174,6 @@ static void read_mc_regs(struct amd64_pvt *pvt) amd64_read_dct_pci_cfg(pvt, 1, DCHR0, &pvt->dchr1); } -skip: - - determine_ecc_sym_sz(pvt); } @@ -3658,7 +3649,7 @@ static int dct_hw_info_get(struct amd64_pvt *pvt) dct_prep_chip_selects(pvt); dct_read_base_mask(pvt); - read_mc_regs(pvt); + dct_read_mc_regs(pvt); dct_determine_memory_type(pvt); return 0; @@ -3672,7 +3663,7 @@ static int umc_hw_info_get(struct amd64_pvt *pvt) umc_prep_chip_selects(pvt); umc_read_base_mask(pvt); - read_mc_regs(pvt); + umc_read_mc_regs(pvt); umc_determine_memory_type(pvt); return 0;