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Fri, 17 Mar 2023 09:15:16 -0500 Received: from xhdshubhraj40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Fri, 17 Mar 2023 09:15:13 -0500 From: Shubhrajyoti Datta To: CC: , , , , , , , , Subject: [PATCH v5 1/2] dt-bindings: edac: Add support for Xilinx Versal EDAC for DDRMC Date: Fri, 17 Mar 2023 19:45:08 +0530 Message-ID: <20230317141509.17534-2-shubhrajyoti.datta@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230317141509.17534-1-shubhrajyoti.datta@amd.com> References: <20230317141509.17534-1-shubhrajyoti.datta@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000C97C:EE_|DS0PR12MB8368:EE_ X-MS-Office365-Filtering-Correlation-Id: b3f6c7c8-3f0d-420d-b747-08db26f208f6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: tUcZeji9dlt/R3ehQCHYym/atDKPhF/1iPegLHKGbRaZgJjOrM7ilNDZyoyvNPNyVNbF7xXatSTQVFDcdMDZ27Qg5xiyR/T+UfAn3SWK4LG38Gt1rDmWm9mBMPt+2bQf2qrEdqpwMN0Bgr4NdpKI9S+mNl9RxTHLf4+XyZzpVJ1x9NkDhvyWQkQzL36uMH89frJAo57fOOa4obdaw1R2JHvD2MaudIImChO8D+AdLFJUkcHm+Z4numNopL9hwESf8IW8zGQK/DnR9cHlcaSSPx018ZBgY4BUkXKyqnNgbvWvic3salbo5coDPOPhI69l4CFgC+AVLozjbbalhGqRx4wSDtGeh4VDTkAaoRs0v6jeWObk/GSSL3UFNPSM5YbsB6OFCHP8VtCqoHwx9EnpXuMbA0yGeikbDt/mmdf6/qHwmMO6pZV60w7WNqUXL5gOO7RdFkw3KvUV1bRtJaWHWxxZk71D7v/J+nHZCAq12r6pJcMyc7TSO2/emHlRb3lZ+gqDCeq+l0OQZKevPBIZN4PspHYEV/J26OyYhUmsriLdjzmq39HZ4YW8lg8e5Uoe4IeD/fgRMSLjs6ine9uEpksM1UA1RAx1axMetjCS2TefDWzX2F8bykM/p6xUSLYWu9LX9w7mfxVzwjJQ1no5N4EsB4F2S/CYM+jN5/rCX4byBF4pEt55AT1yiUavgtEJUBliaLTz1ho1/hN9EMNOdWJPSWH62/pzr3uAPoZpL5F7/Zi5/ik/Xa9si1kcfAYGgSbduW1mLd5K7TN0U5Qojg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230025)(4636009)(346002)(376002)(39860400002)(396003)(136003)(451199018)(36840700001)(46966006)(40470700004)(8936002)(44832011)(5660300002)(4326008)(41300700001)(6916009)(36860700001)(356005)(36756003)(86362001)(40480700001)(82310400005)(40460700003)(82740400003)(81166007)(2906002)(47076005)(966005)(426003)(336012)(6666004)(83380400001)(478600001)(2616005)(186003)(1076003)(26005)(54906003)(70586007)(70206006)(316002)(8676002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2023 14:15:17.6447 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b3f6c7c8-3f0d-420d-b747-08db26f208f6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000C97C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8368 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Add device tree bindings for Xilinx Versal EDAC for DDR controller. Reviewed-by: Krzysztof Kozlowski Co-developed-by: Sai Krishna Potthuri Signed-off-by: Sai Krishna Potthuri Signed-off-by: Shubhrajyoti Datta --- (no changes since v2) Changes in v2: remove edac from compatible Update the description update the ddrmc_base and ddrmc_noc_base names .../xlnx,versal-ddrmc-edac.yaml | 57 +++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml b/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml new file mode 100644 index 000000000000..12f8e9f350bc --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-ddrmc-edac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Versal DDRMC (Integrated DDR Memory Controller) + +maintainers: + - Shubhrajyoti Datta + - Sai Krishna Potthuri + +description: + The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and LPDDR4/ + 4X memory interfaces. Versal DDR memory controller has an optional ECC support + which correct single bit ECC errors and detect double bit ECC errors. + +properties: + compatible: + const: xlnx,versal-ddrmc + + reg: + items: + - description: DDR Memory Controller registers + - description: NOC registers corresponding to DDR Memory Controller + + reg-names: + items: + - const: base + - const: noc + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - interrupts + +additionalProperties: false + +examples: + - | + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + memory-controller@f6150000 { + compatible = "xlnx,versal-ddrmc"; + reg = <0x0 0xf6150000 0x0 0x2000>, <0x0 0xf6070000 0x0 0x20000>; + reg-names = "base", "noc"; + interrupt-parent = <&gic>; + interrupts = ; + }; + };