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Mon, 20 Mar 2023 04:34:13 -0500 Received: from xhdshubhraj40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Mon, 20 Mar 2023 04:34:10 -0500 From: Shubhrajyoti Datta To: CC: , , , , , , , , Subject: [PATCH v6 1/2] dt-bindings: edac: Add support for Xilinx Versal EDAC for DDRMC Date: Mon, 20 Mar 2023 15:04:05 +0530 Message-ID: <20230320093406.2045-2-shubhrajyoti.datta@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230320093406.2045-1-shubhrajyoti.datta@amd.com> References: <20230320093406.2045-1-shubhrajyoti.datta@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT026:EE_|MW4PR12MB6876:EE_ X-MS-Office365-Filtering-Correlation-Id: a24f267f-5d34-465c-ca26-08db2926467c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 0A7awPz3y16kDBJR0jrW0MN5Gdr9Ff10E2G5NQQP3GHn7ZABp6rKyZ9s1pbLRO8vt33uk7arOU6FOgoSzmvpTgni2qLAivU/paiSW+Kdr78IrKdmFk6oH50cjx43qTSfWT6deESgMx8zi+FmHHTLhLNK333ngWk3mjROEg6m7PxJg0+B6ZzYun5tw3IWQjX0mZtYV96Mr0bXUEyTdSDrEjctmCPGh6z87IfoioK06LNHBtn5Wq5g5fZ4hMJSZ/d8GQfQpP05Uz9neE9O7yzSroJC5TwV3D/zT/MkRMVDEQcBINH/qZhZcTtePh8QFwtNiRZD3IHrhUjA8UxJOWl3+/uMa9VHbVMEbb8fZqZEfb05M6NxouMwoGdZoncHDh4rKOHxTHfZ+oBwk08NSbPiL/1hCwLaVI5/Lho6VKRDFGJVhMueb28yt/cIW8QXTEN2HUZ+u9aZoVoqYYQJle4Vmakt+/18Xm18gstQ4r0a67l4Dptqdo46Al2R/Io1k2L/G9P7bVsxhhD3pCafCJfvzcDpfTOp+TBBe1BvWUBs5vCQikiwMgKg4Z7ZdeztnPrL1+eV0KmROwmm1RnVL4FUFEtvAhOJ0C2NP5IwedYE0X2GqwHYwErV79xnbyEz+o1g6w5GwdiAZGcq94H19/RAfl5hqznnQbCD4cuAerGErzKhvSfzfM7C3Hske3GtC0FyKOfTyX/8JRV/VGca8lz/K4llz6ulhKRF7aXnvgmfOAAN2WpifQgFu+/ivt7yTIRJ/+n0wTj30hbQ0K8OM2CeRQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230025)(4636009)(136003)(396003)(39860400002)(376002)(346002)(451199018)(36840700001)(46966006)(40470700004)(356005)(81166007)(86362001)(36756003)(82740400003)(36860700001)(2906002)(41300700001)(44832011)(8936002)(5660300002)(40480700001)(82310400005)(336012)(4326008)(1076003)(54906003)(47076005)(316002)(2616005)(186003)(26005)(426003)(83380400001)(6666004)(8676002)(6916009)(966005)(478600001)(70206006)(70586007)(40460700003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Mar 2023 09:34:16.9574 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a24f267f-5d34-465c-ca26-08db2926467c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT026.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB6876 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Add device tree bindings for Xilinx Versal EDAC for DDR controller. Reviewed-by: Krzysztof Kozlowski Co-developed-by: Sai Krishna Potthuri Signed-off-by: Sai Krishna Potthuri Signed-off-by: Shubhrajyoti Datta --- (no changes since v2) Changes in v2: remove edac from compatible Update the description update the ddrmc_base and ddrmc_noc_base names .../xlnx,versal-ddrmc-edac.yaml | 57 +++++++++++++++++++ 1 file changed, 57 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml b/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml new file mode 100644 index 000000000000..12f8e9f350bc --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-ddrmc-edac.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-ddrmc-edac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Versal DDRMC (Integrated DDR Memory Controller) + +maintainers: + - Shubhrajyoti Datta + - Sai Krishna Potthuri + +description: + The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and LPDDR4/ + 4X memory interfaces. Versal DDR memory controller has an optional ECC support + which correct single bit ECC errors and detect double bit ECC errors. + +properties: + compatible: + const: xlnx,versal-ddrmc + + reg: + items: + - description: DDR Memory Controller registers + - description: NOC registers corresponding to DDR Memory Controller + + reg-names: + items: + - const: base + - const: noc + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - interrupts + +additionalProperties: false + +examples: + - | + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + memory-controller@f6150000 { + compatible = "xlnx,versal-ddrmc"; + reg = <0x0 0xf6150000 0x0 0x2000>, <0x0 0xf6070000 0x0 0x20000>; + reg-names = "base", "noc"; + interrupt-parent = <&gic>; + interrupts = ; + }; + };