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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Apr 2023 20:34:10.6340 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f240aca0-ce3b-471c-71d1-08db3a02f0c4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0000EE3E.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7954 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The "L0" cache level is listed as "reserved" in legacy documentation. This has now been defined as "Core" in current documentation for Zen-based systems. Update the cache level strings to include this new definition. Signed-off-by: Yazen Ghannam --- drivers/edac/mce_amd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c index cc5c63feb26a..1d1b9da3b9bd 100644 --- a/drivers/edac/mce_amd.c +++ b/drivers/edac/mce_amd.c @@ -37,7 +37,7 @@ EXPORT_SYMBOL_GPL(amd_unregister_ecc_decoder); static const char * const tt_msgs[] = { "INSN", "DATA", "GEN", "RESV" }; /* cache level */ -static const char * const ll_msgs[] = { "RESV", "L1", "L2", "L3/GEN" }; +static const char * const ll_msgs[] = { "CORE", "L1", "L2", "L3/GEN" }; /* memory transaction type */ static const char * const rrrr_msgs[] = {