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Tue, 16 May 2023 20:24:54 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT054.mail.protection.outlook.com (10.13.177.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6411.15 via Frontend Transport; Tue, 16 May 2023 20:24:54 +0000 Received: from quartz-7b1chost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Tue, 16 May 2023 15:24:49 -0500 From: Yazen Ghannam To: CC: , , , , , , , , , , , , Yazen Ghannam Subject: [PATCH 5/6] hwmon: (k10temp) Define helper function to read CCD temp Date: Tue, 16 May 2023 15:24:29 -0500 Message-ID: <20230516202430.4157216-6-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230516202430.4157216-1-yazen.ghannam@amd.com> References: <20230516202430.4157216-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT054:EE_|PH7PR12MB6788:EE_ X-MS-Office365-Filtering-Correlation-Id: fc937b06-58b2-4076-da8b-08db564b9c17 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 May 2023 20:24:54.4089 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fc937b06-58b2-4076-da8b-08db564b9c17 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT054.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6788 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The CCD temperature register is read in two places. These reads are done using an AMD SMN access, and a number of parameters are needed for the operation. Move the SMN access and parameter gathering into a helper function in order to simply the code flow. This also has a benefit of centralizing the hardware register access in a single place in case fixes or special decoding is required. Signed-off-by: Yazen Ghannam --- drivers/hwmon/k10temp.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c index 6ea1fa62b7c1..06af1fe38af7 100644 --- a/drivers/hwmon/k10temp.c +++ b/drivers/hwmon/k10temp.c @@ -150,6 +150,18 @@ static void read_tempreg_nb_zen(struct pci_dev *pdev, u32 *regval) *regval = 0; } +static int read_ccd_temp_reg(struct k10temp_data *data, int ccd, u32 *regval) +{ + u16 node_id = amd_pci_dev_to_node_id(data->pdev); + u32 tmp; + + if (amd_smn_read(node_id, ZEN_CCD_TEMP(data->ccd_offset, ccd), &tmp)) + return -EINVAL; + + *regval = tmp; + return 0; +} + static long get_raw_temp(struct k10temp_data *data) { u32 regval; @@ -214,9 +226,7 @@ static int k10temp_read_temp(struct device *dev, u32 attr, int channel, *val = 0; break; case 2 ... 13: /* Tccd{1-12} */ - if (amd_smn_read(amd_pci_dev_to_node_id(data->pdev), - ZEN_CCD_TEMP(data->ccd_offset, channel - 2), - ®val)) + if (read_ccd_temp_reg(data, channel - 2, ®val)) return -EINVAL; *val = (regval & ZEN_CCD_TEMP_MASK) * 125 - 49000; @@ -376,8 +386,7 @@ static void k10temp_get_ccd_support(struct pci_dev *pdev, int i; for (i = 0; i < limit; i++) { - if (amd_smn_read(amd_pci_dev_to_node_id(pdev), - ZEN_CCD_TEMP(data->ccd_offset, i), ®val)) + if (read_ccd_temp_reg(data, i, ®val)) continue; if (regval & ZEN_CCD_TEMP_VALID)