From patchwork Thu Jun 15 16:03:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yazen Ghannam X-Patchwork-Id: 13281451 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7ECEC001DC for ; Thu, 15 Jun 2023 16:03:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234359AbjFOQDu (ORCPT ); Thu, 15 Jun 2023 12:03:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50058 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230003AbjFOQDs (ORCPT ); Thu, 15 Jun 2023 12:03:48 -0400 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2062b.outbound.protection.outlook.com [IPv6:2a01:111:f400:fe59::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5D73A2952; Thu, 15 Jun 2023 09:03:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=L/DvrMV6vbx/c/8jGJWFbr0ALy1WeGWLCxwdCuDwJZpIy5S3JubgBcH2JmAYXXSCOg5SDbniZP8ncm/CRdfYuNrlG6ns4IVzE3nj0JH/jQ3alR6nexAm4VQyHnBR1SpRZi2oE4LDsbzG2MkBz5Qkd/x+5UXRbZGmfzpNIuhl6skV8T0G1KyoKUxu6cPVMQTT1ba5n7/T6EYGjPC0seLZ+i6F7KaZPOgDbcU2WrL5UvvGH+rMeJZdvncVXYYxhfZHXNhbXMDhTO1yWQLgmlNIGGNmdP383aspSbXZpXuqjFTaMfNudEDVFN7Z0H0GD0Upvfgae6qECJyuKg+NJhk8fw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=hZm/z+tvSvGNN5IQANLWkWGEA83rebFjqmt6TDUAujM=; b=NDQH4FlIwzHwe6ZTy2wd57BMB8XEDMeejQIXfjWCQVH7tYuOHJjTNlbmnqP+/3HnrheKBPl4upF/kq3CW2nPZiugwbCbZXYfBZtk2aigc6DSbhnhUZIP1zbm7w3BgB1tZM9ChPEjVXwFj5jWNxmw4/DkV5WjDxXZwd+9ob95ph65Zbnh38Knqe8BMt3gqY1rjk50EB/KHRyh2n8dh81FAlYAZ4jfrPvw0UyGCZJqgMiHtU/CipM+HqvSTIM2JkUwZp/6ul5bdbIwBouW0Giesiv0/7C/GKUe+5Wba+J/oxaAoSPzNYjYe3XZ6vcGXQQxn/RN7bK9sb0nCEuYJ0N6eg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=hZm/z+tvSvGNN5IQANLWkWGEA83rebFjqmt6TDUAujM=; b=oEtYNsd76B0q3wGlpWlX/U2AYxftaMJu6ldqX2OMkMEQwFLlfi8sNkHu/+fMqiIPDHt9KTYgop1VLT31hROwywftQkbgN9puUSAw/ZQb9p3cCzNPYaaG0Y/9bZi8i1RlHdfEiMGpxc7ljh67Daf/xHJvx405EgCtCZ+ovjgaB2Q= Received: from BY5PR03CA0003.namprd03.prod.outlook.com (2603:10b6:a03:1e0::13) by DM6PR12MB4057.namprd12.prod.outlook.com (2603:10b6:5:213::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6477.37; Thu, 15 Jun 2023 16:03:43 +0000 Received: from MWH0EPF000989EC.namprd02.prod.outlook.com (2603:10b6:a03:1e0:cafe::69) by BY5PR03CA0003.outlook.office365.com (2603:10b6:a03:1e0::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6477.37 via Frontend Transport; Thu, 15 Jun 2023 16:03:43 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by MWH0EPF000989EC.mail.protection.outlook.com (10.167.241.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6500.27 via Frontend Transport; Thu, 15 Jun 2023 16:03:43 +0000 Received: from quartz-7b1chost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Thu, 15 Jun 2023 11:03:42 -0500 From: Yazen Ghannam To: CC: , , , , , , , , , , , , Yazen Ghannam Subject: [PATCH v2 2/6] EDAC/amd64: Check return value of amd_smn_read() Date: Thu, 15 Jun 2023 11:03:24 -0500 Message-ID: <20230615160328.419610-3-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230615160328.419610-1-yazen.ghannam@amd.com> References: <20230615160328.419610-1-yazen.ghannam@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000989EC:EE_|DM6PR12MB4057:EE_ X-MS-Office365-Filtering-Correlation-Id: c450d177-244b-4726-5b32-08db6dba17f5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 8ss4n9MgNnOeAq9z6ibOdEdPodbx+JbQDmcFgp0UcsAeDlurRpaRJTG/NTXCbL4DGqLDVcKeJYpXxDd9zfaD94fpC30FXfZg6NuKIqVdLjVKuAPK4b3KATo5uW00fqqHBb5sLXOlEemkmwiX0wXDhKnagD0e/k49tfbSrc+IbjkF/h3Wl3YTQSrgCak9CAFXLdbGPSUddW3jCiTgptVTi8x2e83dlxBB8EYbVaL4hp1E4lt1t06Mc/S4ZCc2jqopSBwfyToyQD6P2yI4VTlaYuSPVAOBCzMbRKy1L30cfrKZsYcd3riXyj72shYGX4rkJG9evHPPLDIncFuXZPrxvJAWP4WJhCdsunJ8f9X2fH6Lcyg87h0YSKBff81YEMs9RM7t0Nd1Qpb7wvKQ25YqXI0v9T+fnftoqgxUs9Ah28OQfOwGDALamLUKgpQ9IIXHhmrq3hDYTl477IYR2ZiLm0Qy9pLEwcl5FvSYdyZbNKOAEGVXKpmKgIDyD8jTmd5FNjg0gui1fhX/3pVReC62iIYJIlsGeAvzkc6Aej0sTLP6Gfxwgy8IT38WTShppvNl1Nf6kNWna8iYHeeB7HiasbvLE+jJVZUZS94VHPgArLHu2874ngE+0T8/CsjWIJ12wjxt5ujGyHmiUdPxAuTSjH8huCoFeiHTnLWYb2ZUxsuCgE2FTJCSzhVekWYQrXwNOZoYyvNVdYmvz1zVQrfzYPkb+scXUPpXJExoRdyi0wNmhyXmR7CypZTLI3gvqPPQgfXFwVO6ylyRf41BlRtMwA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(39860400002)(136003)(376002)(346002)(396003)(451199021)(36840700001)(46966006)(40470700004)(1076003)(26005)(36756003)(186003)(16526019)(478600001)(966005)(40480700001)(6666004)(40460700003)(7696005)(2906002)(316002)(41300700001)(8936002)(44832011)(86362001)(81166007)(8676002)(5660300002)(356005)(82740400003)(7416002)(83380400001)(336012)(82310400005)(54906003)(47076005)(426003)(2616005)(6916009)(70206006)(70586007)(4326008)(36860700001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jun 2023 16:03:43.4951 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c450d177-244b-4726-5b32-08db6dba17f5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000989EC.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4057 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Check the return value of amd_smn_read() before saving a value. This ensures invalid values aren't saved. The struct umc instance is initialized to 0 during memory allocation. Therefore, a bad read will keep the value as 0 providing the expected Read-as-Zero behavior. Furthermore, the __must_check attribute will be added to amd_smn_read(). Therefore, this change is required to avoid compile-time warnings. Signed-off-by: Yazen Ghannam Cc: stable@vger.kernel.org --- Link: https://lore.kernel.org/r/20230516202430.4157216-3-yazen.ghannam@amd.com v1->v2: * Include amd_smd_read() calls added for GPU updates. drivers/edac/amd64_edac.c | 51 ++++++++++++++++++++++++++++----------- 1 file changed, 37 insertions(+), 14 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 67feebc1eafe..4f6c31c193d8 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1703,6 +1703,7 @@ static void umc_read_base_mask(struct amd64_pvt *pvt) u32 *base, *base_sec; u32 *mask, *mask_sec; int cs, umc; + u32 tmp; for_each_umc(umc) { umc_base_reg = get_umc_base(umc) + UMCCH_BASE_ADDR; @@ -1715,13 +1716,17 @@ static void umc_read_base_mask(struct amd64_pvt *pvt) base_reg = umc_base_reg + (cs * 4); base_reg_sec = umc_base_reg_sec + (cs * 4); - if (!amd_smn_read(pvt->mc_node_id, base_reg, base)) + if (!amd_smn_read(pvt->mc_node_id, base_reg, &tmp)) { + *base = tmp; edac_dbg(0, " DCSB%d[%d]=0x%08x reg: 0x%x\n", umc, cs, *base, base_reg); + } - if (!amd_smn_read(pvt->mc_node_id, base_reg_sec, base_sec)) + if (!amd_smn_read(pvt->mc_node_id, base_reg_sec, &tmp)) { + *base_sec = tmp; edac_dbg(0, " DCSB_SEC%d[%d]=0x%08x reg: 0x%x\n", umc, cs, *base_sec, base_reg_sec); + } } umc_mask_reg = get_umc_base(umc) + UMCCH_ADDR_MASK; @@ -1734,13 +1739,17 @@ static void umc_read_base_mask(struct amd64_pvt *pvt) mask_reg = umc_mask_reg + (cs * 4); mask_reg_sec = umc_mask_reg_sec + (cs * 4); - if (!amd_smn_read(pvt->mc_node_id, mask_reg, mask)) + if (!amd_smn_read(pvt->mc_node_id, mask_reg, &tmp)) { + *mask = tmp; edac_dbg(0, " DCSM%d[%d]=0x%08x reg: 0x%x\n", umc, cs, *mask, mask_reg); + } - if (!amd_smn_read(pvt->mc_node_id, mask_reg_sec, mask_sec)) + if (!amd_smn_read(pvt->mc_node_id, mask_reg_sec, &tmp)) { + *mask_sec = tmp; edac_dbg(0, " DCSM_SEC%d[%d]=0x%08x reg: 0x%x\n", umc, cs, *mask_sec, mask_reg_sec); + } } } } @@ -3153,7 +3162,7 @@ static void umc_read_mc_regs(struct amd64_pvt *pvt) { u8 nid = pvt->mc_node_id; struct amd64_umc *umc; - u32 i, umc_base; + u32 i, tmp, umc_base; /* Read registers from each UMC */ for_each_umc(i) { @@ -3161,11 +3170,20 @@ static void umc_read_mc_regs(struct amd64_pvt *pvt) umc_base = get_umc_base(i); umc = &pvt->umc[i]; - amd_smn_read(nid, umc_base + get_umc_reg(pvt, UMCCH_DIMM_CFG), &umc->dimm_cfg); - amd_smn_read(nid, umc_base + UMCCH_UMC_CFG, &umc->umc_cfg); - amd_smn_read(nid, umc_base + UMCCH_SDP_CTRL, &umc->sdp_ctrl); - amd_smn_read(nid, umc_base + UMCCH_ECC_CTRL, &umc->ecc_ctrl); - amd_smn_read(nid, umc_base + UMCCH_UMC_CAP_HI, &umc->umc_cap_hi); + if (!amd_smn_read(nid, umc_base + get_umc_reg(pvt, UMCCH_DIMM_CFG), &tmp)) + umc->dimm_cfg = tmp; + + if (!amd_smn_read(nid, umc_base + UMCCH_UMC_CFG, &tmp)) + umc->umc_cfg = tmp; + + if (!amd_smn_read(nid, umc_base + UMCCH_SDP_CTRL, &tmp)) + umc->sdp_ctrl = tmp; + + if (!amd_smn_read(nid, umc_base + UMCCH_ECC_CTRL, &tmp)) + umc->ecc_ctrl = tmp; + + if (!amd_smn_read(nid, umc_base + UMCCH_UMC_CAP_HI, &tmp)) + umc->umc_cap_hi = tmp; } } @@ -3891,16 +3909,21 @@ static void gpu_read_mc_regs(struct amd64_pvt *pvt) { u8 nid = pvt->mc_node_id; struct amd64_umc *umc; - u32 i, umc_base; + u32 i, tmp, umc_base; /* Read registers from each UMC */ for_each_umc(i) { umc_base = gpu_get_umc_base(i, 0); umc = &pvt->umc[i]; - amd_smn_read(nid, umc_base + UMCCH_UMC_CFG, &umc->umc_cfg); - amd_smn_read(nid, umc_base + UMCCH_SDP_CTRL, &umc->sdp_ctrl); - amd_smn_read(nid, umc_base + UMCCH_ECC_CTRL, &umc->ecc_ctrl); + if (!amd_smn_read(nid, umc_base + UMCCH_UMC_CFG, &tmp)) + umc->umc_cfg = tmp; + + if (!amd_smn_read(nid, umc_base + UMCCH_SDP_CTRL, &tmp)) + umc->sdp_ctrl = tmp; + + if (!amd_smn_read(nid, umc_base + UMCCH_ECC_CTRL, &tmp)) + umc->ecc_ctrl = tmp; } }