| Message ID | 20230706171323.3722900-3-avadhut.naik@amd.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Updates for AMD Family 1Ah-based Models | expand |
On 7/6/23 10:13, Avadhut Naik wrote: > From: Avadhut Naik <Avadhut.Naik@amd.com> > > Add thermal info support for AMD Family 1Ah-based models. Support is > provided on a per-socket granularity. > > Co-developed-by: Mario Limonciello <mario.limonciello@amd.com> > Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> > Signed-off-by: Avadhut Naik <Avadhut.Naik@amd.com> Acked-by: Guenter Roeck <linux@roeck-us.net> > --- > drivers/hwmon/k10temp.c | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c > index 7b177b9fbb09..c61837fbc315 100644 > --- a/drivers/hwmon/k10temp.c > +++ b/drivers/hwmon/k10temp.c > @@ -65,7 +65,7 @@ static DEFINE_MUTEX(nb_smu_ind_mutex); > #define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET 0xd8200c64 > #define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4 > > -/* Common for Zen CPU families (Family 17h and 18h and 19h) */ > +/* Common for Zen CPU families (Family 17h and 18h and 19h and 1Ah) */ > #define ZEN_REPORTED_TEMP_CTRL_BASE 0x00059800 > > #define ZEN_CCD_TEMP(offset, x) (ZEN_REPORTED_TEMP_CTRL_BASE + \ > @@ -462,6 +462,10 @@ static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id) > k10temp_get_ccd_support(pdev, data, 12); > break; > } > + } else if (boot_cpu_data.x86 == 0x1a) { > + data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK; > + data->read_tempreg = read_tempreg_nb_zen; > + data->is_zen = true; > } else { > data->read_htcreg = read_htcreg_pci; > data->read_tempreg = read_tempreg_pci; > @@ -508,6 +512,8 @@ static const struct pci_device_id k10temp_id_table[] = { > { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M60H_DF_F3) }, > { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M70H_DF_F3) }, > { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M78H_DF_F3) }, > + { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_1AH_M00H_DF_F3) }, > + { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_1AH_M20H_DF_F3) }, > { PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) }, > {} > };
diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c index 7b177b9fbb09..c61837fbc315 100644 --- a/drivers/hwmon/k10temp.c +++ b/drivers/hwmon/k10temp.c @@ -65,7 +65,7 @@ static DEFINE_MUTEX(nb_smu_ind_mutex); #define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET 0xd8200c64 #define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4 -/* Common for Zen CPU families (Family 17h and 18h and 19h) */ +/* Common for Zen CPU families (Family 17h and 18h and 19h and 1Ah) */ #define ZEN_REPORTED_TEMP_CTRL_BASE 0x00059800 #define ZEN_CCD_TEMP(offset, x) (ZEN_REPORTED_TEMP_CTRL_BASE + \ @@ -462,6 +462,10 @@ static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id) k10temp_get_ccd_support(pdev, data, 12); break; } + } else if (boot_cpu_data.x86 == 0x1a) { + data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK; + data->read_tempreg = read_tempreg_nb_zen; + data->is_zen = true; } else { data->read_htcreg = read_htcreg_pci; data->read_tempreg = read_tempreg_pci; @@ -508,6 +512,8 @@ static const struct pci_device_id k10temp_id_table[] = { { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M60H_DF_F3) }, { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M70H_DF_F3) }, { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M78H_DF_F3) }, + { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_1AH_M00H_DF_F3) }, + { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_1AH_M20H_DF_F3) }, { PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) }, {} };