| Message ID | 20231215053352.8740-1-shubhrajyoti.datta@amd.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v3] EDAC/versal: Fix the read of the num_csrows and num_chans | expand |
On Fri, Dec 15, 2023 at 11:03:52AM +0530, Shubhrajyoti Datta wrote: > Fix the extraction of the num_csrows and num_chans. > The extraction of the num_rows is wrong. Instead of extracting > using the FIELD_GET it is calling FIELD_PREP. > > The issue was masked as the default design has the rows as 0. > > Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> > Closes: https://lore.kernel.org/all/60ca157e-6eff-d12c-9dc0-8aeab125edda@linux-m68k.org/ > Fixes: 6f15b178cd63 ("EDAC/versal: Add a Xilinx Versal memory controller driver") > Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> > --- > > Changes in v3: > Update the commit message > > Changes in v2: > Update the commit message > > drivers/edac/versal_edac.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/edac/versal_edac.c b/drivers/edac/versal_edac.c > index 87e20f39f999..f0d8702802a1 100644 > --- a/drivers/edac/versal_edac.c > +++ b/drivers/edac/versal_edac.c > @@ -1038,10 +1038,10 @@ static int mc_probe(struct platform_device *pdev) > edac_mc_id = emif_get_id(pdev->dev.of_node); > > regval = readl(ddrmc_baseaddr + XDDR_REG_CONFIG0_OFFSET); > - num_chans = FIELD_PREP(XDDR_REG_CONFIG0_NUM_CHANS_MASK, regval); > + num_chans = FIELD_GET(XDDR_REG_CONFIG0_NUM_CHANS_MASK, regval); > num_chans++; > > - num_csrows = FIELD_PREP(XDDR_REG_CONFIG0_NUM_RANKS_MASK, regval); > + num_csrows = FIELD_GET(XDDR_REG_CONFIG0_NUM_RANKS_MASK, regval); > num_csrows *= 2; > if (!num_csrows) > num_csrows = 1; > -- Applied, thanks.
diff --git a/drivers/edac/versal_edac.c b/drivers/edac/versal_edac.c index 87e20f39f999..f0d8702802a1 100644 --- a/drivers/edac/versal_edac.c +++ b/drivers/edac/versal_edac.c @@ -1038,10 +1038,10 @@ static int mc_probe(struct platform_device *pdev) edac_mc_id = emif_get_id(pdev->dev.of_node); regval = readl(ddrmc_baseaddr + XDDR_REG_CONFIG0_OFFSET); - num_chans = FIELD_PREP(XDDR_REG_CONFIG0_NUM_CHANS_MASK, regval); + num_chans = FIELD_GET(XDDR_REG_CONFIG0_NUM_CHANS_MASK, regval); num_chans++; - num_csrows = FIELD_PREP(XDDR_REG_CONFIG0_NUM_RANKS_MASK, regval); + num_csrows = FIELD_GET(XDDR_REG_CONFIG0_NUM_RANKS_MASK, regval); num_csrows *= 2; if (!num_csrows) num_csrows = 1;
Fix the extraction of the num_csrows and num_chans. The extraction of the num_rows is wrong. Instead of extracting using the FIELD_GET it is calling FIELD_PREP. The issue was masked as the default design has the rows as 0. Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> Closes: https://lore.kernel.org/all/60ca157e-6eff-d12c-9dc0-8aeab125edda@linux-m68k.org/ Fixes: 6f15b178cd63 ("EDAC/versal: Add a Xilinx Versal memory controller driver") Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> --- Changes in v3: Update the commit message Changes in v2: Update the commit message drivers/edac/versal_edac.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)