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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 May 2024 15:57:02.0917 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 65c67d38-8160-4493-0336-08dc7b40fc56 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF00004680.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4318 AMD systems optionally support MCA thresholding. This feature is discovered by checking capability bits in the MCA_MISC* registers. Currently, MCA thresholding is set up in two passes. The first is during CPU init where available banks are detected, and the "bank_map" variable is updated. The second is during sysfs/device init when the thresholding data structures are allocated and hardware is fully configured. During device init, the "threshold_banks" array is allocated even if no available banks were discovered. Furthermore, the thresholding reset flow checks if the top-level "threshold_banks" array is non-NULL, but it doesn't check if individual "threshold_bank" structures are non-NULL. This is avoided because the hardware interrupt is not enabled in this case. But this issue becomes present if enabling the interrupt when the thresholding data structures are not initialized. Check "bank_map" to determine if the thresholding structures should be allocated and initialized. Also, remove "mce_flags.amd_threshold" which is redundant when checking "bank_map". Signed-off-by: Yazen Ghannam --- arch/x86/kernel/cpu/mce/amd.c | 2 +- arch/x86/kernel/cpu/mce/core.c | 1 - arch/x86/kernel/cpu/mce/internal.h | 5 +---- 3 files changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 9a0133ef7e20..d7dee59cc1ca 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -1395,7 +1395,7 @@ int mce_threshold_create_device(unsigned int cpu) struct threshold_bank **bp; int err; - if (!mce_flags.amd_threshold) + if (!this_cpu_read(bank_map)) return 0; bp = this_cpu_read(threshold_banks); diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 704e651203b4..58b8efdcec0b 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -1984,7 +1984,6 @@ static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c) mce_flags.overflow_recov = !!cpu_has(c, X86_FEATURE_OVERFLOW_RECOV); mce_flags.succor = !!cpu_has(c, X86_FEATURE_SUCCOR); mce_flags.smca = !!cpu_has(c, X86_FEATURE_SMCA); - mce_flags.amd_threshold = 1; } } diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/internal.h index 01f8f03969e6..08571b10bf3f 100644 --- a/arch/x86/kernel/cpu/mce/internal.h +++ b/arch/x86/kernel/cpu/mce/internal.h @@ -214,9 +214,6 @@ struct mce_vendor_flags { /* Zen IFU quirk */ zen_ifu_quirk : 1, - /* AMD-style error thresholding banks present. */ - amd_threshold : 1, - /* Pentium, family 5-style MCA */ p5 : 1, @@ -229,7 +226,7 @@ struct mce_vendor_flags { /* Skylake, Cascade Lake, Cooper Lake REP;MOVS* quirk */ skx_repmov_quirk : 1, - __reserved_0 : 55; + __reserved_0 : 56; }; extern struct mce_vendor_flags mce_flags;