EDAC/ie31200: Add more device IDs

Commit Message

Takuya Wakazono July 18, 2024, 2:14 a.m. UTC

We verified that the following CPUs can detect errors when single-bit
and multi-bit errors occur: 1614, 1900, 3e10, 3ec4

Signed-off-by: Takuya Wakazono <[e-mail]>
---
 drivers/edac/ie31200_edac.c | 42 ++++++++++++++++++++++++-------------
 1 file changed, 27 insertions(+), 15 deletions(-)

Patch

diff --git a/drivers/edac/ie31200_edac.c b/drivers/edac/ie31200_edac.c
index 9ef13570f2e5..8c5a4ae54364 100644
--- a/drivers/edac/ie31200_edac.c
+++ b/drivers/edac/ie31200_edac.c
@@ -18,6 +18,8 @@ 
  * 015c: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller
  * 0c04: Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller
  * 0c08: Xeon E3-1200 v3 Processor DRAM Controller
+ * 1614: Broadwell-U Host Bridge - DMI 
+ * 1900: Xeon E3-1200 v5/E3-1500 v5/6th Gen Core Processor Host Bridge/DRAM Registers
  * 1918: Xeon E3-1200 v5 Skylake Host Bridge/DRAM Registers
  * 5918: Xeon E3-1200 Xeon E3-1200 v6/7th Gen Core Processor Host Bridge/DRAM Registers
  * 190f: 6th Gen Core Dual-Core Processor Host Bridge/DRAM Registers
@@ -27,6 +29,7 @@ 
  * Based on Intel specification:
  * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v3-vol-2-datasheet.pdf
  * http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200-family-vol-2-datasheet.html
+ * https://www.intel.com/content/www/us/en/content-details/332379/mobile-5th-generation-intel-core-processor-datasheet-vol-2.html
  * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/desktop-6th-gen-core-family-datasheet-vol-2.pdf
  * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v6-vol-2-datasheet.pdf
  * https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-h-processor-lines-datasheet-vol-2.html
@@ -64,30 +67,35 @@ 
 #define PCI_DEVICE_ID_INTEL_IE31200_HB_5  0x015c
 #define PCI_DEVICE_ID_INTEL_IE31200_HB_6  0x0c04
 #define PCI_DEVICE_ID_INTEL_IE31200_HB_7  0x0c08
-#define PCI_DEVICE_ID_INTEL_IE31200_HB_8  0x190F
-#define PCI_DEVICE_ID_INTEL_IE31200_HB_9  0x1918
-#define PCI_DEVICE_ID_INTEL_IE31200_HB_10 0x191F
-#define PCI_DEVICE_ID_INTEL_IE31200_HB_11 0x5918
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_8  0x1614
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_9  0x1900
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_10 0x190F
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_11 0x1918
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_12 0x191F
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_13 0x5918
 
 /* Coffee Lake-S */
 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK 0x3e00
 #define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_1    0x3e0f
-#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_2    0x3e18
-#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_3    0x3e1f
-#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_4    0x3e30
-#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_5    0x3e31
-#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_6    0x3e32
-#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_7    0x3e33
-#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_8    0x3ec2
-#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_9    0x3ec6
-#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_10   0x3eca
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_2    0x3e10
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_3    0x3e18
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_4    0x3e1f
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_5    0x3e30
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_6    0x3e31
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_7    0x3e32
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_8    0x3e33
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_9    0x3ec2
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_10   0x3ec4
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_11   0x3ec6
+#define PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_12   0x3eca
 
 /* Test if HB is for Skylake or later. */
 #define DEVICE_ID_SKYLAKE_OR_LATER(did)                                        \
-	(((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_8) ||                        \
-	 ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_9) ||                        \
+	(((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_9) ||                        \
 	 ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_10) ||                       \
 	 ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_11) ||                       \
+	 ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_12) ||                       \
+	 ((did) == PCI_DEVICE_ID_INTEL_IE31200_HB_13) ||                       \
 	 (((did) & PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK) ==                 \
 	  PCI_DEVICE_ID_INTEL_IE31200_HB_CFL_MASK))
 
@@ -587,6 +595,8 @@  static const struct pci_device_id ie31200_pci_tbl[] = {
 	{ PCI_VEND_DEV(INTEL, IE31200_HB_9),      PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
 	{ PCI_VEND_DEV(INTEL, IE31200_HB_10),     PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
 	{ PCI_VEND_DEV(INTEL, IE31200_HB_11),     PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
+	{ PCI_VEND_DEV(INTEL, IE31200_HB_12),     PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
+	{ PCI_VEND_DEV(INTEL, IE31200_HB_13),     PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
 	{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_1),  PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
 	{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_2),  PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
 	{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_3),  PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
@@ -597,6 +607,8 @@  static const struct pci_device_id ie31200_pci_tbl[] = {
 	{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_8),  PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
 	{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_9),  PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
 	{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_10), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
+	{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_11), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
+	{ PCI_VEND_DEV(INTEL, IE31200_HB_CFL_12), PCI_ANY_ID, PCI_ANY_ID, 0, 0, IE31200 },
 	{ 0, } /* 0 terminated list. */
 };
 MODULE_DEVICE_TABLE(pci, ie31200_pci_tbl);