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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN3PEPF0000B071.mail.protection.outlook.com (10.167.243.116) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7918.13 via Frontend Transport; Thu, 29 Aug 2024 22:32:39 +0000 Received: from quartz-7b1chost.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 29 Aug 2024 17:32:37 -0500 From: Yazen Ghannam To: CC: , , , , , , Yazen Ghannam Subject: [RFC PATCH v2 1/2] x86/mce: Set a more accurate value for mce_num_banks Date: Thu, 29 Aug 2024 17:32:24 -0500 Message-ID: <20240829223225.223639-2-yazen.ghannam@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240829223225.223639-1-yazen.ghannam@amd.com> References: <20240829223225.223639-1-yazen.ghannam@amd.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B071:EE_|BL3PR12MB6402:EE_ X-MS-Office365-Filtering-Correlation-Id: e6599003-d6cd-4d48-1d96-08dcc87a7d53 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: wedm+p8uNWZXzjqdQjB0fiRczaZHWbdYiT56vytNePiQ8o+RxVOOwuWlxFrdxtjtsdk/c44FgtsPD/cvzHB2IymR4JaOtImbILNd1AO6y/DLZJwNCHOFGC59Ktt4qeVG4pIaGMX6B8r+l+teI4RfmnLe5NzsEK82tMIrUXeAbm0h+1qdhktxugYfsRF+K14Qfx0ytV3vs342c2aH6pVnLw15BP34DQtxhj+7k+Me+79s01LTF5jGuqrq2lLiT5/Obq1E7TTI7CuxgdgPsXWNGNBuhQ+mfyckYl4yI7LMKJeqh62RPTlg4frM3Izaj1jBysVEUSrmREhZdVkNiKnBsojj7fZkaatiFO14xD2tO/ua1w9VwqWADXgBp5IL/NVNOzQyfncLE6ltdZVjrBbyvVMWhwhn28VLfjDMS/qDQwyDK6p0TRmIFlfI01N0JIEdKf7KnVMeSNVVRt1qZo/f+bRYU7aHJZrWcsZLjbYWrSOG2xg3KXSxysmC4lezLnyT5IEBbQfr+XFdHMb2AQQzrrKEorHzDFNT0FLQJgIAwr2HbzBqowrvt4pCJdJZfdTAEPfDU5VucgbQ9kgb51qG6TkLan6vONWWZZlmBYhjn3xNFLguV8nUmHj4XNwDsDsyYHsxubv/UHywGqAznlk3aZAA4QuDUHZ360ROD2jyqJMMEwWBlsqItl58uYJV4FX6fU2DJWkRxDpJqOUxFhPkgWcYNac1Z6bz8VqYcG97+uqm6iW4lMW6ne6UrptX1o5ONy3rsAie5E7y0DTmNASj/f3UUYgVmvefEwcTilbngsejiUntboLuvuNovUr0KvypkJfc+DGQo4LhIgCqMU4onf7LFwz3IF6lqwVNlsRqxpC2NCwLFXHYuidCRrrsaQ6Jt53N3J+b1+4TbEdFwKJVjTAhtMT/56tfR/mtFCehuWVzzdbkmkKhGDrimLNEnwILy2CeM+gcKHcXjoE44dbLtqask8yOEBpwAhnesRZ64LTVS4Tdp0kh0aYdMpfcnKhMUZ6pBNVtP61K1zGOrzejPj68HlLwd5f5xSnq98fTyr7z4Tc2ORMdKRccYtqD1t1Tg+cnWlpNOObL17kEA6FBsw2k3hztuHflxC3uk140pt1EeYtonz94Us8JNb8qb7D77aoHbnnSwNJrlDvJettzegdn2jksite0p3JYUefETa8qpDEVG/JOewKXYMaPfAd0H0/D9VZi305V1qF3w9QdKc4pLUJMO1hhw9wJfQIwUrHgdoBlA0Pz335FM6dRGXDmFRZVMrrl8Pld+VkuyKPHMlaYmTn/kEvhA4FaUg2RGFji4Ta6ctJb1Ls16kPsQWGPjGEaKeINSKImYnTsSbLfYiyMYgKfzAAlbq2/51naJf8jBGNN9X2pmawIL6yskCQAgHhYH4cHrZsscHxXW12rrDK5uekA6SMGIZ0rhtvui7Y5AjmJFSdCgxwa4rt0S17P X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(376014)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Aug 2024 22:32:39.1744 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e6599003-d6cd-4d48-1d96-08dcc87a7d53 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B071.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6402 Some systems advertise more MCA banks than are actually used. For example, MCG_CAP[Count] gives 64 banks, but banks 32-63 are not used, i.e. Read-as-Zero/Writes-Ignored. This causes more time spent checking, or trying to setup, banks that are not used. Currently, valid banks are already checked for during initialization. Extend this to keep track of the last valid bank found and update mce_num_banks to reflect this. Signed-off-by: Yazen Ghannam --- arch/x86/kernel/cpu/mce/core.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 2a938f429c4d..33893b5c8b0c 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -1866,8 +1866,8 @@ static void __mcheck_cpu_init_clear_banks(void) static void __mcheck_cpu_check_banks(void) { struct mce_bank *mce_banks = this_cpu_ptr(mce_banks_array); + int i, last_bank; u64 msrval; - int i; for (i = 0; i < this_cpu_read(mce_num_banks); i++) { struct mce_bank *b = &mce_banks[i]; @@ -1877,7 +1877,12 @@ static void __mcheck_cpu_check_banks(void) rdmsrl(mca_msr_reg(i, MCA_CTL), msrval); b->init = !!msrval; + + if (b->init) + last_bank = i; } + + this_cpu_write(mce_num_banks, last_bank + 1); } /* Add per CPU specific workarounds here */