| Message ID | 20240918055436.15551-2-TonyWWang-oc@zhaoxin.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | x86/mce: Add Zhaoxin MCE support | expand |
On Wed, Sep 18, 2024 at 01:54:34PM +0800, Tony W Wang-oc wrote: > From: Lyle Li <LyleLi@zhaoxin.com> > > Zhaoxin consists of two vendors, X86_VENDOR_ZHAOXIN and > X86_VENDOR_CENTAUR, so add the centaur vendor to support > Zhaoxin MCA in mce/core.c and mce/intel.c. > > Signed-off-by: Lyle Li <LyleLi@zhaoxin.com> > Signed-off-by: Tony W Wang-oc <TonyWWang-oc@zhaoxin.com> > --- > arch/x86/kernel/cpu/mce/core.c | 12 +++++++++--- > arch/x86/kernel/cpu/mce/intel.c | 3 ++- > 2 files changed, 11 insertions(+), 4 deletions(-) > > diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c > index ad0623b65..7f79d900f 100644 > --- a/arch/x86/kernel/cpu/mce/core.c > +++ b/arch/x86/kernel/cpu/mce/core.c > @@ -496,6 +496,7 @@ bool mce_usable_address(struct mce *m) > > case X86_VENDOR_INTEL: > case X86_VENDOR_ZHAOXIN: > + case X86_VENDOR_CENTAUR: > return intel_mce_usable_address(m); > > default: > @@ -513,6 +514,7 @@ bool mce_is_memory_error(struct mce *m) > > case X86_VENDOR_INTEL: > case X86_VENDOR_ZHAOXIN: > + case X86_VENDOR_CENTAUR: > /* > * Intel SDM Volume 3B - 15.9.2 Compound Error Codes > * > @@ -1247,7 +1249,8 @@ static noinstr bool mce_check_crashing_cpu(void) > > mcgstatus = __rdmsr(MSR_IA32_MCG_STATUS); > > - if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) { > + if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN || > + boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR) { > if (mcgstatus & MCG_STATUS_LMCES) > return false; > } > @@ -1521,7 +1524,8 @@ noinstr void do_machine_check(struct pt_regs *regs) > * on Intel, Zhaoxin only. > */ > if (m.cpuvendor == X86_VENDOR_INTEL || > - m.cpuvendor == X86_VENDOR_ZHAOXIN) > + m.cpuvendor == X86_VENDOR_ZHAOXIN || > + m.cpuvendor == X86_VENDOR_CENTAUR) > lmce = m.mcgstatus & MCG_STATUS_LMCES; > > /* > @@ -2092,6 +2096,7 @@ static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c) > break; > > case X86_VENDOR_ZHAOXIN: > + case X86_VENDOR_CENTAUR: > mce_zhaoxin_feature_clear(c); > break; > > @@ -2401,7 +2406,8 @@ static void vendor_disable_error_reporting(void) > if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL || > boot_cpu_data.x86_vendor == X86_VENDOR_HYGON || > boot_cpu_data.x86_vendor == X86_VENDOR_AMD || > - boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) > + boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN || > + boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR) > return; > > mce_disable_error_reporting(); At this point, should we even do this? It seems all major vendors want to *not* disable MCA_CTL after init. This, and related functions, can be deleted. Unless there's a compelling reason to keep them. Thanks, Yazen
On 2024/9/19 21:55, Yazen Ghannam wrote: > > On Wed, Sep 18, 2024 at 01:54:34PM +0800, Tony W Wang-oc wrote: >> From: Lyle Li <LyleLi@zhaoxin.com> >> >> Zhaoxin consists of two vendors, X86_VENDOR_ZHAOXIN and >> X86_VENDOR_CENTAUR, so add the centaur vendor to support >> Zhaoxin MCA in mce/core.c and mce/intel.c. >> >> Signed-off-by: Lyle Li <LyleLi@zhaoxin.com> >> Signed-off-by: Tony W Wang-oc <TonyWWang-oc@zhaoxin.com> >> --- >> arch/x86/kernel/cpu/mce/core.c | 12 +++++++++--- >> arch/x86/kernel/cpu/mce/intel.c | 3 ++- >> 2 files changed, 11 insertions(+), 4 deletions(-) >> >> diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c >> index ad0623b65..7f79d900f 100644 >> --- a/arch/x86/kernel/cpu/mce/core.c >> +++ b/arch/x86/kernel/cpu/mce/core.c >> @@ -496,6 +496,7 @@ bool mce_usable_address(struct mce *m) >> >> case X86_VENDOR_INTEL: >> case X86_VENDOR_ZHAOXIN: >> + case X86_VENDOR_CENTAUR: >> return intel_mce_usable_address(m); >> >> default: >> @@ -513,6 +514,7 @@ bool mce_is_memory_error(struct mce *m) >> >> case X86_VENDOR_INTEL: >> case X86_VENDOR_ZHAOXIN: >> + case X86_VENDOR_CENTAUR: >> /* >> * Intel SDM Volume 3B - 15.9.2 Compound Error Codes >> * >> @@ -1247,7 +1249,8 @@ static noinstr bool mce_check_crashing_cpu(void) >> >> mcgstatus = __rdmsr(MSR_IA32_MCG_STATUS); >> >> - if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) { >> + if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN || >> + boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR) { >> if (mcgstatus & MCG_STATUS_LMCES) >> return false; >> } >> @@ -1521,7 +1524,8 @@ noinstr void do_machine_check(struct pt_regs *regs) >> * on Intel, Zhaoxin only. >> */ >> if (m.cpuvendor == X86_VENDOR_INTEL || >> - m.cpuvendor == X86_VENDOR_ZHAOXIN) >> + m.cpuvendor == X86_VENDOR_ZHAOXIN || >> + m.cpuvendor == X86_VENDOR_CENTAUR) >> lmce = m.mcgstatus & MCG_STATUS_LMCES; >> >> /* >> @@ -2092,6 +2096,7 @@ static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c) >> break; >> >> case X86_VENDOR_ZHAOXIN: >> + case X86_VENDOR_CENTAUR: >> mce_zhaoxin_feature_clear(c); >> break; >> >> @@ -2401,7 +2406,8 @@ static void vendor_disable_error_reporting(void) >> if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL || >> boot_cpu_data.x86_vendor == X86_VENDOR_HYGON || >> boot_cpu_data.x86_vendor == X86_VENDOR_AMD || >> - boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) >> + boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN || >> + boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR) >> return; >> >> mce_disable_error_reporting(); > > At this point, should we even do this? It seems all major vendors want > to *not* disable MCA_CTL after init. > > This, and related functions, can be deleted. Unless there's a compelling > reason to keep them. > From the current code implementation, your suggestion is reasonable. Will delete the related functions in the next version. Sincerely TonyWWang-oc
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index ad0623b65..7f79d900f 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -496,6 +496,7 @@ bool mce_usable_address(struct mce *m) case X86_VENDOR_INTEL: case X86_VENDOR_ZHAOXIN: + case X86_VENDOR_CENTAUR: return intel_mce_usable_address(m); default: @@ -513,6 +514,7 @@ bool mce_is_memory_error(struct mce *m) case X86_VENDOR_INTEL: case X86_VENDOR_ZHAOXIN: + case X86_VENDOR_CENTAUR: /* * Intel SDM Volume 3B - 15.9.2 Compound Error Codes * @@ -1247,7 +1249,8 @@ static noinstr bool mce_check_crashing_cpu(void) mcgstatus = __rdmsr(MSR_IA32_MCG_STATUS); - if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) { + if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN || + boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR) { if (mcgstatus & MCG_STATUS_LMCES) return false; } @@ -1521,7 +1524,8 @@ noinstr void do_machine_check(struct pt_regs *regs) * on Intel, Zhaoxin only. */ if (m.cpuvendor == X86_VENDOR_INTEL || - m.cpuvendor == X86_VENDOR_ZHAOXIN) + m.cpuvendor == X86_VENDOR_ZHAOXIN || + m.cpuvendor == X86_VENDOR_CENTAUR) lmce = m.mcgstatus & MCG_STATUS_LMCES; /* @@ -2092,6 +2096,7 @@ static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 *c) break; case X86_VENDOR_ZHAOXIN: + case X86_VENDOR_CENTAUR: mce_zhaoxin_feature_clear(c); break; @@ -2401,7 +2406,8 @@ static void vendor_disable_error_reporting(void) if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL || boot_cpu_data.x86_vendor == X86_VENDOR_HYGON || boot_cpu_data.x86_vendor == X86_VENDOR_AMD || - boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) + boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN || + boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR) return; mce_disable_error_reporting(); diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c index f6103e6bf..b7e67f4f7 100644 --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -88,7 +88,8 @@ static int cmci_supported(int *banks) * makes sure none of the backdoors are entered otherwise. */ if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL && - boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN) + boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN && + boot_cpu_data.x86_vendor != X86_VENDOR_CENTAUR) return 0; if (!boot_cpu_has(X86_FEATURE_APIC) || lapic_get_maxlvt() < 6)