From patchwork Thu Dec 12 14:00:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhuo, Qiuxu" X-Patchwork-Id: 13905234 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 75C4A2AF0E; Thu, 12 Dec 2024 14:02:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734012179; cv=none; b=kndVHT+/YGAs+r63eQVAGkMm1idtVp8y7BXWkHCtA7kpFxWXS45+/JLpotRr2NZUzUe8b4VYjVq9kV4CJRxdzdMbyn9jmPbPJoyMrjtljqDNKadopoEwXQofdHNwFHJSfCpTSwxQjsBMOFogIqQh1XdedN4oIWULQKsUEQ6EyyE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1734012179; c=relaxed/simple; bh=DmdYTP32GF7FMD0V8FptK4pVHw0QjiNU7SvaxwERjtE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References; b=QJuGx2QJmmH+8fneYyXSj6WOyUTxclOUWdjOj9fgSCBJ7rNx2ZmdRMO6XKisEqhqi9VItP0CR8YMzfErfY022oiT4QUdDoIj1TOJOWGmAuoNbfqZPc+y2IlNABfs9yJDzkL3WImOJFjz2kh62QqQ5xX0VX+VEBxsbCrrrUPdRUo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=ePL0ia6f; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="ePL0ia6f" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1734012178; x=1765548178; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=DmdYTP32GF7FMD0V8FptK4pVHw0QjiNU7SvaxwERjtE=; b=ePL0ia6fgSW0L3Z1R11mE4m9OXA/0ixRFYwlCEaI1hBsDG8EkmW102Wh cypaweGnb8V4Ccv43uTLEutUm7uYI+M7s0vnfnaVXMd2rZhW2eKV864r/ 5SUY4p5LWwippQuzzH4ddHt2az5AuRsD4BnBPXNav478WMxG/WBWERUso Z+8R4WWD+obg5wzrJb1LByTaGgI/t2UkHs/xZzDj4b0x5/uaBGi44i7vn ZXaRc3YU7korLJGgSB/oSdP4h2rwHuK7BT+ZQoI1Zk5qRZkroBcFQwDqZ m1fUuQduB4ybz05GEUdG5vLkTnsCEYLSBXOkBoxlcNajjhvbu8DfwfLCv Q==; X-CSE-ConnectionGUID: oiIFklUfTeaa22CstmnMIA== X-CSE-MsgGUID: n4yMmg0SSneF8NhRIX49+g== X-IronPort-AV: E=McAfee;i="6700,10204,11284"; a="34154972" X-IronPort-AV: E=Sophos;i="6.12,228,1728975600"; d="scan'208";a="34154972" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Dec 2024 06:02:56 -0800 X-CSE-ConnectionGUID: 6srgGy58StuaSWtLR+dUzA== X-CSE-MsgGUID: VF+k8lvQRUqjGbfzCYmcAQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,228,1728975600"; d="scan'208";a="96465385" Received: from qiuxu-clx.sh.intel.com ([10.239.53.109]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Dec 2024 06:02:53 -0800 From: Qiuxu Zhuo To: bp@alien8.de, tony.luck@intel.com Cc: tglx@linutronix.de, dave.hansen@linux.intel.com, mingo@redhat.com, hpa@zytor.com, yazen.ghannam@amd.com, sohil.mehta@intel.com, nik.borisov@suse.com, x86@kernel.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, qiuxu.zhuo@intel.com Subject: [PATCH v5 1/7] x86/mce: Make several functions return bool Date: Thu, 12 Dec 2024 22:00:57 +0800 Message-Id: <20241212140103.66964-2-qiuxu.zhuo@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241212140103.66964-1-qiuxu.zhuo@intel.com> References: <20241111060428.44258-1-qiuxu.zhuo@intel.com> <20241212140103.66964-1-qiuxu.zhuo@intel.com> Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Make several functions that return 0 or 1 return a boolean value for better readability. No functional changes are intended. Reviewed-by: Tony Luck Reviewed-by: Nikolay Borisov Reviewed-by: Sohil Mehta Signed-off-by: Qiuxu Zhuo Reviewed-by: Yazen Ghannam --- Changes in v5: - No changes. Changes in v4: - Don't rename mce_notify_irq() - Boris. Changes in v3: - Collect "Reviewed-by:" from Nikolay & Sohil. - Rename mce_notify_irq() to mce_notify_user() (Sohil). Changes in v2: - Collect "Reviewed-by:" from Tony. arch/x86/include/asm/mce.h | 4 ++-- arch/x86/kernel/cpu/mce/amd.c | 10 +++++----- arch/x86/kernel/cpu/mce/core.c | 22 +++++++++++----------- arch/x86/kernel/cpu/mce/intel.c | 9 +++++---- 4 files changed, 23 insertions(+), 22 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 4543cf2eb5e8..ea9ca7689f6b 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -276,7 +276,7 @@ static inline void cmci_rediscover(void) {} static inline void cmci_recheck(void) {} #endif -int mce_available(struct cpuinfo_x86 *c); +bool mce_available(struct cpuinfo_x86 *c); bool mce_is_memory_error(struct mce *m); bool mce_is_correctable(struct mce *m); bool mce_usable_address(struct mce *m); @@ -296,7 +296,7 @@ enum mcp_flags { void machine_check_poll(enum mcp_flags flags, mce_banks_t *b); -int mce_notify_irq(void); +bool mce_notify_irq(void); DECLARE_PER_CPU(struct mce, injectm); diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 6ca80fff1fea..018874b554cb 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -381,7 +381,7 @@ static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits) return msr_high_bits & BIT(28); } -static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) +static bool lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) { int msr = (hi & MASK_LVTOFF_HI) >> 20; @@ -389,7 +389,7 @@ static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt " "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, b->bank, b->block, b->address, hi, lo); - return 0; + return false; } if (apic != msr) { @@ -399,15 +399,15 @@ static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi) * was set is reserved. Return early here: */ if (mce_flags.smca) - return 0; + return false; pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d " "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu, apic, b->bank, b->block, b->address, hi, lo); - return 0; + return false; } - return 1; + return true; }; /* Reprogram MCx_MISC MSR behind this threshold bank. */ diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 7fb5556a0b53..167965bd2ac0 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -492,10 +492,10 @@ static noinstr void mce_gather_info(struct mce_hw_err *err, struct pt_regs *regs } } -int mce_available(struct cpuinfo_x86 *c) +bool mce_available(struct cpuinfo_x86 *c) { if (mca_cfg.disabled) - return 0; + return false; return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA); } @@ -1778,7 +1778,7 @@ static void mce_timer_delete_all(void) * Can be called from interrupt context, but not from machine check/NMI * context. */ -int mce_notify_irq(void) +bool mce_notify_irq(void) { /* Not more than two messages every minute */ static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2); @@ -1789,9 +1789,9 @@ int mce_notify_irq(void) if (__ratelimit(&ratelimit)) pr_info(HW_ERR "Machine check events logged\n"); - return 1; + return true; } - return 0; + return false; } EXPORT_SYMBOL_GPL(mce_notify_irq); @@ -2015,25 +2015,25 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c) return 0; } -static int __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) +static bool __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c) { if (c->x86 != 5) - return 0; + return false; switch (c->x86_vendor) { case X86_VENDOR_INTEL: intel_p5_mcheck_init(c); mce_flags.p5 = 1; - return 1; + return true; case X86_VENDOR_CENTAUR: winchip_mcheck_init(c); mce_flags.winchip = 1; - return 1; + return true; default: - return 0; + return false; } - return 0; + return false; } /* diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c index b3cd2c61b11d..f863df0ff42c 100644 --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -75,12 +75,12 @@ static u16 cmci_threshold[MAX_NR_BANKS]; */ #define CMCI_STORM_THRESHOLD 32749 -static int cmci_supported(int *banks) +static bool cmci_supported(int *banks) { u64 cap; if (mca_cfg.cmci_disabled || mca_cfg.ignore_ce) - return 0; + return false; /* * Vendor check is not strictly needed, but the initial @@ -89,10 +89,11 @@ static int cmci_supported(int *banks) */ if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL && boot_cpu_data.x86_vendor != X86_VENDOR_ZHAOXIN) - return 0; + return false; if (!boot_cpu_has(X86_FEATURE_APIC) || lapic_get_maxlvt() < 6) - return 0; + return false; + rdmsrl(MSR_IA32_MCG_CAP, cap); *banks = min_t(unsigned, MAX_NR_BANKS, cap & MCG_BANKCNT_MASK); return !!(cap & MCG_CMCI_P);