| Message ID | 20250213-wip-mca-updates-v2-8-3636547fe05f@amd.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | AMD MCA interrupts rework | expand |
> From: Yazen Ghannam <yazen.ghannam@amd.com> > Sent: Friday, February 14, 2025 12:46 AM > To: x86@kernel.org; Luck, Tony <tony.luck@intel.com> > Cc: linux-kernel@vger.kernel.org; linux-edac@vger.kernel.org; > Smita.KoralahalliChannabasappa@amd.com; Yazen Ghannam > <yazen.ghannam@amd.com> > Subject: [PATCH v2 08/16] x86/mce: Define BSP-only SMCA init > > Currently on AMD systems, MCA interrupt handler functions are set during > CPU init. However, the functions only need to be set once for the whole > system. > > Assign the handlers only during BSP init. Do so only for SMCA systems to > maintain the old behavior for legacy systems. Looks like the interrupt handler is still set during each per-CPU online, right? What's the benefit/purpose of this patch? Thanks! mce_cpu_online(cpu) mce_threshold_create_device(cpu) { ... mce_threshold_vector = amd_threshold_interrupt; ... } > Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> [...]
On Tue, Feb 18, 2025 at 03:33:08AM +0000, Zhuo, Qiuxu wrote: > > From: Yazen Ghannam <yazen.ghannam@amd.com> > > Sent: Friday, February 14, 2025 12:46 AM > > To: x86@kernel.org; Luck, Tony <tony.luck@intel.com> > > Cc: linux-kernel@vger.kernel.org; linux-edac@vger.kernel.org; > > Smita.KoralahalliChannabasappa@amd.com; Yazen Ghannam > > <yazen.ghannam@amd.com> > > Subject: [PATCH v2 08/16] x86/mce: Define BSP-only SMCA init > > > > Currently on AMD systems, MCA interrupt handler functions are set during > > CPU init. However, the functions only need to be set once for the whole > > system. > > > > Assign the handlers only during BSP init. Do so only for SMCA systems to > > maintain the old behavior for legacy systems. > > Looks like the interrupt handler is still set during each per-CPU online, right? > What's the benefit/purpose of this patch? Thanks! > This patch is doing the "correct" thing. > mce_cpu_online(cpu) > mce_threshold_create_device(cpu) { > ... > mce_threshold_vector = amd_threshold_interrupt; > ... > } > This part remains for legacy systems. However, I think this is another place to do more cleanup later. Thanks, Yazen
diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index a4ef4ff1a7ff..bf2b1dc5aaa9 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -687,6 +687,12 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) deferred_error_interrupt_enable(c); } +void mce_smca_cpu_init(void) +{ + mce_threshold_vector = amd_threshold_interrupt; + deferred_error_int_vector = amd_deferred_error_interrupt; +} + /* * DRAM ECC errors are reported in the Northbridge (bank 4) with * Extended Error Code 8. diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index f13d3f7ca56e..402d7993eb96 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -2243,6 +2243,9 @@ void cpu_mca_init(struct cpuinfo_x86 *c) mce_flags.succor = cpu_feature_enabled(X86_FEATURE_SUCCOR); mce_flags.smca = cpu_feature_enabled(X86_FEATURE_SMCA); + if (mce_flags.smca) + mce_smca_cpu_init(); + rdmsrl(MSR_IA32_MCG_CAP, cap); /* Use accurate RIP reporting if available. */ diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/internal.h index 231ba8ca4a3e..a4bae8c0cf4c 100644 --- a/arch/x86/kernel/cpu/mce/internal.h +++ b/arch/x86/kernel/cpu/mce/internal.h @@ -293,11 +293,13 @@ static __always_inline void smca_extract_err_addr(struct mce *m) m->addr &= GENMASK_ULL(55, lsb); } +void mce_smca_cpu_init(void); #else static inline void mce_threshold_create_device(unsigned int cpu) { } static inline bool amd_filter_mce(struct mce *m) { return false; } static inline bool amd_mce_usable_address(struct mce *m) { return false; } static inline void smca_extract_err_addr(struct mce *m) { } +static inline void mce_smca_cpu_init(void) {} #endif #ifdef CONFIG_X86_ANCIENT_MCE
Currently on AMD systems, MCA interrupt handler functions are set during CPU init. However, the functions only need to be set once for the whole system. Assign the handlers only during BSP init. Do so only for SMCA systems to maintain the old behavior for legacy systems. Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com> --- Notes: Link: https://lore.kernel.org/r/20240604154635.GTZl8222q7WAEVSJKH@fat_crate.local v1->v2: * New in v2. arch/x86/kernel/cpu/mce/amd.c | 6 ++++++ arch/x86/kernel/cpu/mce/core.c | 3 +++ arch/x86/kernel/cpu/mce/internal.h | 2 ++ 3 files changed, 11 insertions(+)