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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CH2PEPF00000146.mail.protection.outlook.com (10.167.244.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8655.12 via Frontend Transport; Tue, 15 Apr 2025 14:55:18 +0000 Received: from [127.0.1.1] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 15 Apr 2025 09:55:17 -0500 From: Yazen Ghannam Date: Tue, 15 Apr 2025 14:55:10 +0000 Subject: [PATCH v3 15/17] x86/mce/amd: Support SMCA Corrected Error Interrupt Precedence: bulk X-Mailing-List: linux-edac@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-ID: <20250415-wip-mca-updates-v3-15-8ffd9eb4aa56@amd.com> References: <20250415-wip-mca-updates-v3-0-8ffd9eb4aa56@amd.com> In-Reply-To: <20250415-wip-mca-updates-v3-0-8ffd9eb4aa56@amd.com> To: , Tony Luck CC: , , , Qiuxu Zhuo X-Mailer: b4 0.15-dev-9b767 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000146:EE_|BY5PR12MB4099:EE_ X-MS-Office365-Filtering-Correlation-Id: db9c5556-9b29-4b72-ae2d-08dd7c2d8a04 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|376014|13003099007; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Apr 2025 14:55:18.6788 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: db9c5556-9b29-4b72-ae2d-08dd7c2d8a04 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000146.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4099 AMD systems optionally support MCA thresholding which provides the ability for hardware to send an interrupt when a set error threshold is reached. This feature counts errors of all severities, but it is commonly used to report correctable errors with an interrupt rather than polling. Scalable MCA systems allow the Platform to take control of this feature. In this case, the OS will not see the feature configuration and control bits in the MCA_MISC* registers. The OS will not receive the MCA thresholding interrupt, and it will need to poll for correctable errors. A "corrected error interrupt" will be available on Scalable MCA systems. This will be used in the same configuration where the Platform controls MCA thresholding. However, the Platform will now be able to send the MCA thresholding interrupt to the OS. Check for the feature bit in the MCA_CONFIG register and confirm that the MCA thresholding interrupt handler is already enabled. If successful, set the feature enable bit in the MCA_CONFIG register to indicate to the Platform that the OS is ready for the interrupt. Tested-by: Tony Luck Reviewed-by: Tony Luck Signed-off-by: Yazen Ghannam --- Notes: Link: https://lore.kernel.org/r/20250213-wip-mca-updates-v2-15-3636547fe05f@amd.com v2->v3: * Add tags from Tony. v1->v2: * Use new per-CPU struct. arch/x86/kernel/cpu/mce/amd.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 9e226bdbdc40..d76a64c47a6d 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -306,6 +306,11 @@ static void smca_configure(unsigned int bank, unsigned int cpu) high |= BIT(5); } + if ((low & BIT(10)) && data->thr_intr_en) { + __set_bit(bank, data->thr_intr_banks); + high |= BIT(8); + } + this_cpu_ptr(mce_banks_array)[bank].lsb_in_status = !!(low & BIT(8)); wrmsr(smca_config, low, high);