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([2001:4898:80e8:7:6421:7c91:4399:b8b2]) by smtp.gmail.com with ESMTPSA id 8sm10976987pfc.42.2019.11.17.18.10.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 17 Nov 2019 18:10:43 -0800 (PST) To: bp@alien8.de, james.morse@arm.com, robh+dt@kernel.org, mark.rutland@arm.com From: Shiping Ji Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mchehab@kernel.org, linux-edac@vger.kernel.org, sashal@kernel.org, hangl@microsoft.com, lewan@microsoft.com, ruizhao@microsoft.com, scott.branden@broadcom.com, yuqing.shen@broadcom.com, ray.jui@broadcom.com, shji@microsoft.com, wangglei@gmail.com Subject: [PATCH v7 1/2] dt-bindings: edac: arm-dmc520.txt Message-ID: Date: Sun, 17 Nov 2019 18:10:43 -0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.2.2 MIME-Version: 1.0 Content-Language: en-US Sender: linux-edac-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org This is the device tree bindings for new EDAC driver dmc520_edac.c. Signed-off-by: Lei Wang Reviewed-by: James Morse --- Changes in v7: - Added arm prefix to the interrupt-config property --- .../devicetree/bindings/edac/arm-dmc520.txt | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 Documentation/devicetree/bindings/edac/arm-dmc520.txt diff --git a/Documentation/devicetree/bindings/edac/arm-dmc520.txt b/Documentation/devicetree/bindings/edac/arm-dmc520.txt new file mode 100644 index 000000000000..476cf8b76f2a --- /dev/null +++ b/Documentation/devicetree/bindings/edac/arm-dmc520.txt @@ -0,0 +1,26 @@ +* ARM DMC-520 EDAC node + +Required properties: +- compatible : "brcm,dmc-520", "arm,dmc-520". +- reg : Address range of the DMC-520 registers. +- interrupts : DMC-520 interrupt numbers. The example below specifies + two interrupt lines for dram_ecc_errc_int and + dram_ecc_errd_int. +- arm,interrupt-config : This is an array of interrupt masks. For each of the + above interrupt line, add one interrupt mask element to + it. That is, there is a 1:1 mapping from each interrupt + line to an interrupt mask. An interrupt mask can represent + multiple interrupts being enabled. Refer to interrupt_control + register in DMC-520 TRM for interrupt mapping. In the example + below, the interrupt configuration enables dram_ecc_errc_int + and dram_ecc_errd_int. And each interrupt is connected to + a separate interrupt line. + +Example: + +dmc0: dmc@200000 { + compatible = "brcm,dmc-520", "arm,dmc-520"; + reg = <0x200000 0x80000>; + interrupts = <0x0 0x349 0x4>, <0x0 0x34B 0x4>; + arm,interrupt-config = <0x4>, <0x8>; +};