From patchwork Mon Nov 5 07:44:25 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jingoo Han X-Patchwork-Id: 1695321 Return-Path: X-Original-To: patchwork-linux-fbdev@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id EF7FC3FCDE for ; Mon, 5 Nov 2012 07:44:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751704Ab2KEHod (ORCPT ); Mon, 5 Nov 2012 02:44:33 -0500 Received: from mailout2.samsung.com ([203.254.224.25]:27253 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751210Ab2KEHoc (ORCPT ); Mon, 5 Nov 2012 02:44:32 -0500 Received: from epcpsbgm2.samsung.com (epcpsbgm2 [203.254.230.27]) by mailout2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MD000D52856FLV0@mailout2.samsung.com> for linux-fbdev@vger.kernel.org; Mon, 05 Nov 2012 16:44:25 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [203.254.230.47]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 90.B3.12699.95E67905; Mon, 05 Nov 2012 16:44:25 +0900 (KST) X-AuditID: cbfee61b-b7f616d00000319b-3c-50976e59bcac Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 40.B3.12699.95E67905; Mon, 05 Nov 2012 16:44:25 +0900 (KST) Received: from DOJG1HAN02 ([12.23.120.99]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MD0002L7861I070@mmp1.samsung.com> for linux-fbdev@vger.kernel.org; Mon, 05 Nov 2012 16:44:25 +0900 (KST) From: Jingoo Han To: 'Florian Tobias Schandinat' Cc: linux-fbdev@vger.kernel.org, 'Ajay Kumar' , 'Jingoo Han' References: In-reply-to: Subject: [PATCH v3 2/2] video: exynos_dp: Fix incorrect setting for INT_CTL Date: Mon, 05 Nov 2012 16:44:25 +0900 Message-id: <003401cdbb29$60b46220$221d2660$%han@samsung.com> MIME-version: 1.0 Content-type: text/plain; charset=us-ascii Content-transfer-encoding: 7bit X-Mailer: Microsoft Office Outlook 12.0 Thread-index: Ac27KUIAmX/J1rmES6qj/A5auPWLMgAAAO4w Content-language: ko DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrCIsWRmVeSWpSXmKPExsVy+t8zfd3IvOkBBucOaluc6PvA6sDo8XmT XABjFJdNSmpOZllqkb5dAlfGo7tnmAvecVc8Xn2SpYHxL2cXIyeHhICJxJ7/i9kgbDGJC/fW A9lcHEICyxglzl3YygRT9PXuLVaIxCJGiWN7f0FVzWKSmLOrjxmkik1ATeLLl8PsXYwcHCIC VhKbtmqCmMwCeRIv/qmAmEIC3BKrm4NAijkFeCTW/ekEaxQW8JboPbiCBcRmEVCVaPq7kx3E 5hWwlWj/fIMNwhaU+DH5HlgNs4CWxPqdx5kgbHmJzWveMoOMlxBQl3j0VxckLCJgJHFoyU42 iBIRiX0v3jFCjBeQ+Db5EAtEuazEpgPMIH9ICCxjl7gy8Sc7xLeSEgdX3GCZwCgxC8nmWUg2 z0KyeRaSFQsYWVYxiqYWJBcUJ6XnGukVJ+YWl+al6yXn525ihESV9A7GVQ0WhxgFOBiVeHg/ SUwPEGJNLCuuzD3EKMHBrCTCy8EAFOJNSaysSi3Kjy8qzUktPsToA3T5RGYp0eR8YMTnlcQb GhubmJmYmphbmpqb4hBWEudt9kgJEBJITyxJzU5NLUgtghnHxMEp1cDoYXfnGmv8xmsr/eXT DWVrM6zW3XXOcZhg19rzU37R/mPXnrN7Lp7HLnxVf0ay0aHJS2aYMlmodkUHJr2aGfr6/qQz AclLpP70JC9a277846kHqsfPi+w/k7rrfXvDH8Z9HXfX3+A9+N3yZfjcCTL3v79Onfvue+kl uQtrvTZGOLj8vHzh1FEVGyWW4oxEQy3mouJEAG3u81PXAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrMIsWRmVeSWpSXmKPExsVy+t9jAd3IvOkBBm9Wq1uc6PvA6sDo8XmT XABjVAOjTUZqYkpqkUJqXnJ+SmZeuq2Sd3C8c7ypmYGhrqGlhbmSQl5ibqqtkotPgK5bZg7Q VCWFssScUqBQQGJxsZK+HaYJoSFuuhYwjRG6viFBcD1GBmggYR1jxqO7Z5gL3nFXPF59kqWB 8S9nFyMnh4SAicTXu7dYIWwxiQv31rN1MXJxCAksYpQ4tvcXlDOLSWLOrj5mkCo2ATWJL18O s3cxcnCICFhJbNqqCWIyC+RJvPinAmIKCXBLrG4OAinmFOCRWPenE6xRWMBbovfgChYQm0VA VaLp7052EJtXwFai/fMNNghbUOLH5HtgNcwCWhLrdx5ngrDlJTavecsMMl5CQF3i0V9dkLCI gJHEoSU72SBKRCT2vXjHOIFRaBaSSbOQTJqFZNIsJC0LGFlWMYqmFiQXFCel5xrpFSfmFpfm pesl5+duYgTH7DPpHYyrGiwOMQpwMCrx8H6SmB4gxJpYVlyZe4hRgoNZSYSXgwEoxJuSWFmV WpQfX1Sak1p8iNEH6NGJzFKiyfnAdJJXEm9obGJmZGlkZmFkYm6OQ1hJnLfZIyVASCA9sSQ1 OzW1ILUIZhwTB6dUA+OyOXsSPbtkvyxrCK4NKYn9vkRX3/j983KO1Q/O/GbffHXSy/437fbq P4o+pfmy9Cz5uTun+8UP1hVn+Mvj9U1Fr9pW73U6fFUzda5spVtXa8X2feYPxRI+ymrMej3p zRkl3u0FMb+dJ7wTZ9yz3Y3Z5H/0O7ni3oW/FzZ/bV5iZnz7aM3decpKLMUZiYZazEXFiQD2 B3PPBgMAAA== X-CFilter-Loop: Reflected Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org INT_CTL register contains bits INT_POL0 and INT_POL1, and not INT_POL. This patch fixes the wrong register setting for INT_CTL. Signed-off-by: Ajay Kumar Signed-off-by: Jingoo Han --- Tested with Exynos5250 drivers/video/exynos/exynos_dp_reg.c | 2 +- drivers/video/exynos/exynos_dp_reg.h | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/video/exynos/exynos_dp_reg.c b/drivers/video/exynos/exynos_dp_reg.c index 3f5ca8a..cc7765f 100644 --- a/drivers/video/exynos/exynos_dp_reg.c +++ b/drivers/video/exynos/exynos_dp_reg.c @@ -88,7 +88,7 @@ void exynos_dp_init_analog_param(struct exynos_dp_device *dp) void exynos_dp_init_interrupt(struct exynos_dp_device *dp) { /* Set interrupt pin assertion polarity as high */ - writel(INT_POL, dp->reg_base + EXYNOS_DP_INT_CTL); + writel(INT_POL1 | INT_POL0, dp->reg_base + EXYNOS_DP_INT_CTL); /* Clear pending regisers */ writel(0xff, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1); diff --git a/drivers/video/exynos/exynos_dp_reg.h b/drivers/video/exynos/exynos_dp_reg.h index 1f2f014..2e9bd0e 100644 --- a/drivers/video/exynos/exynos_dp_reg.h +++ b/drivers/video/exynos/exynos_dp_reg.h @@ -242,7 +242,8 @@ /* EXYNOS_DP_INT_CTL */ #define SOFT_INT_CTRL (0x1 << 2) -#define INT_POL (0x1 << 0) +#define INT_POL1 (0x1 << 1) +#define INT_POL0 (0x1 << 0) /* EXYNOS_DP_SYS_CTL_1 */ #define DET_STA (0x1 << 2)