From patchwork Mon Nov 5 07:52:42 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jingoo Han X-Patchwork-Id: 1695341 Return-Path: X-Original-To: patchwork-linux-fbdev@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id BFECBDF2AB for ; Mon, 5 Nov 2012 08:00:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753036Ab2KEIAx (ORCPT ); Mon, 5 Nov 2012 03:00:53 -0500 Received: from mailout3.samsung.com ([203.254.224.33]:16446 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753018Ab2KEIAw (ORCPT ); Mon, 5 Nov 2012 03:00:52 -0500 Received: from epcpsbgm1.samsung.com (epcpsbgm1 [203.254.230.26]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MD000EQF8EZCWC0@mailout3.samsung.com> for linux-fbdev@vger.kernel.org; Mon, 05 Nov 2012 16:52:43 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [203.254.230.51]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 45.F9.01231.A4077905; Mon, 05 Nov 2012 16:52:43 +0900 (KST) X-AuditID: cbfee61a-b7fa66d0000004cf-07-5097704a4f37 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id E4.F9.01231.A4077905; Mon, 05 Nov 2012 16:52:42 +0900 (KST) Received: from DOJG1HAN02 ([12.23.120.99]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MD0003U78JUA050@mmp2.samsung.com> for linux-fbdev@vger.kernel.org; Mon, 05 Nov 2012 16:52:42 +0900 (KST) From: Jingoo Han To: 'Florian Tobias Schandinat' Cc: linux-fbdev@vger.kernel.org, 'Ajay Kumar' , 'Jingoo Han' References: <003401cdbb29$60b46220$221d2660$%han@samsung.com> In-reply-to: <003401cdbb29$60b46220$221d2660$%han@samsung.com> Subject: [PATCH v3 2/2] video: exynos_dp: Fix incorrect setting for INT_CTL Date: Mon, 05 Nov 2012 16:52:42 +0900 Message-id: <003c01cdbb2a$8924c000$9b6e4000$%han@samsung.com> MIME-version: 1.0 Content-type: text/plain; charset=us-ascii Content-transfer-encoding: 7bit X-Mailer: Microsoft Office Outlook 12.0 Thread-index: Ac27KUIAmX/J1rmES6qj/A5auPWLMgAAAO4wAABG3VA= Content-language: ko DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrCIsWRmVeSWpSXmKPExsVy+t8zY13vgukBBhfvM1qc6PvA6sDo8XmT XABjFJdNSmpOZllqkb5dAlfGzRVCBbt4Kq5v+sjSwHiAq4uRk0NCwETiQfsKJghbTOLCvfVs XYxcHEICyxgl7q6YxA5TNPnOAqjEdEaJ3QffMEI4s5gkbvVcYQGpYhNQk/jy5TBQBweHiICV xKatmiAms0CexIt/KiAVQgK2Ev/ebQer5hSwk+i78IMRxBYW8JboPbgCLM4ioCrxsXM5K4jN C1T/ZNtpJghbUOLH5HtgNcwCWhLrdx5ngrDlJTavecsMskpCQF3i0V9dkDDIAS97LjJClIhI 7HvxjhFivIDEt8mHWCDKZSU2HWAGeURCYB67xN5bi5kh3pWUOLjiBssERolZSDbPQrJ5FpLN s5CsWMDIsopRNLUguaA4KT3XUK84Mbe4NC9dLzk/dxMjJKqkdjCubLA4xCjAwajEwztTbHqA EGtiWXFl7iFGCQ5mJRFeDgagEG9KYmVValF+fFFpTmrxIUYfoMsnMkuJJucDIz6vJN7Q2NjE zMTUxNzS1NwUh7CSOG+zR0qAkEB6YklqdmpqQWoRzDgmDk6pBsaNrxz6p+V8uOv5oceKp+7v lk1Wne4pswN2nSvf5mDUmPdAotPx8VJ/DckFjZW57hmBPNoadfzsD8M1Si+1Mrn/s681EF61 MGf3M5e9TAW7vjaz2l9IW2flJiho+NwrcKn66bMtiQEsu0Vb/6jH39qc7vpUvS5pT+rl5umu ppxLst7fTGiyV2Ipzkg01GIuKk4EAHza5HXXAgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrMIsWRmVeSWpSXmKPExsVy+t9jQV2vgukBBsdnWFuc6PvA6sDo8XmT XABjVAOjTUZqYkpqkUJqXnJ+SmZeuq2Sd3C8c7ypmYGhrqGlhbmSQl5ibqqtkotPgK5bZg7Q VCWFssScUqBQQGJxsZK+HaYJoSFuuhYwjRG6viFBcD1GBmggYR1jxs0VQgW7eCqub/rI0sB4 gKuLkZNDQsBEYvKdBWwQtpjEhXvrgWwuDiGB6YwSuw++YYRwZjFJ3Oq5wgJSxSagJvHly2H2 LkYODhEBK4lNWzVBTGaBPIkX/1RAKoQEbCX+vdsOVs0pYCfRd+EHI4gtLOAt0XtwBVicRUBV 4mPnclYQmxeo/sm200wQtqDEj8n3wGqYBbQk1u88zgRhy0tsXvOWGWSVhIC6xKO/uiBhkANe 9lxkhCgRkdj34h3jBEahWUgmzUIyaRaSSbOQtCxgZFnFKJpakFxQnJSea6hXnJhbXJqXrpec n7uJERyzz6R2MK5ssDjEKMDBqMTDO1NseoAQa2JZcWXuIUYJDmYlEV4OBqAQb0piZVVqUX58 UWlOavEhRh+gRycyS4km5wPTSV5JvKGxiZmRpZGZhZGJuTkOYSVx3maPlAAhgfTEktTs1NSC 1CKYcUwcnFINjJPM9Z0lOFyPMrULrJ9n03X3RGrAlEtzrOP9eVf/Xzz71LrdIRNXLrY88705 Zv26qNtFeRejE8ODCrLVEzPecFzvE/K7c2Z+dIhEmeOJrO+uc+YW2P15ZKLe1fd7Ke/FR/FX ZkalPmh7mnB8d8fOY2cdX/B/mxE6laWXXUrtr0wyi8GCbPV9FkosxRmJhlrMRcWJALKdSa4G AwAA X-CFilter-Loop: Reflected Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org From: Ajay Kumar INT_CTL register contains bits INT_POL0 and INT_POL1, and not INT_POL. This patch fixes the wrong register setting for INT_CTL. Signed-off-by: Ajay Kumar Signed-off-by: Jingoo Han --- Added 'From: Ajay Kumar ' drivers/video/exynos/exynos_dp_reg.c | 2 +- drivers/video/exynos/exynos_dp_reg.h | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/video/exynos/exynos_dp_reg.c b/drivers/video/exynos/exynos_dp_reg.c index 3f5ca8a..cc7765f 100644 --- a/drivers/video/exynos/exynos_dp_reg.c +++ b/drivers/video/exynos/exynos_dp_reg.c @@ -88,7 +88,7 @@ void exynos_dp_init_analog_param(struct exynos_dp_device *dp) void exynos_dp_init_interrupt(struct exynos_dp_device *dp) { /* Set interrupt pin assertion polarity as high */ - writel(INT_POL, dp->reg_base + EXYNOS_DP_INT_CTL); + writel(INT_POL1 | INT_POL0, dp->reg_base + EXYNOS_DP_INT_CTL); /* Clear pending regisers */ writel(0xff, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1); diff --git a/drivers/video/exynos/exynos_dp_reg.h b/drivers/video/exynos/exynos_dp_reg.h index 1f2f014..2e9bd0e 100644 --- a/drivers/video/exynos/exynos_dp_reg.h +++ b/drivers/video/exynos/exynos_dp_reg.h @@ -242,7 +242,8 @@ /* EXYNOS_DP_INT_CTL */ #define SOFT_INT_CTRL (0x1 << 2) -#define INT_POL (0x1 << 0) +#define INT_POL1 (0x1 << 1) +#define INT_POL0 (0x1 << 0) /* EXYNOS_DP_SYS_CTL_1 */ #define DET_STA (0x1 << 2)