From patchwork Thu Nov 1 10:18:49 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jingoo Han X-Patchwork-Id: 1684211 Return-Path: X-Original-To: patchwork-linux-fbdev@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 0CEF0E003B for ; Thu, 1 Nov 2012 10:18:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753437Ab2KAKSw (ORCPT ); Thu, 1 Nov 2012 06:18:52 -0400 Received: from mailout4.samsung.com ([203.254.224.34]:27044 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750815Ab2KAKSw (ORCPT ); Thu, 1 Nov 2012 06:18:52 -0400 Received: from epcpsbgm1.samsung.com (epcpsbgm1 [203.254.230.26]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MCT002MS0N27QZ0@mailout4.samsung.com> for linux-fbdev@vger.kernel.org; Thu, 01 Nov 2012 19:18:50 +0900 (KST) X-AuditID: cbfee61a-b7fa66d0000004cf-4a-50924c8a1788 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id E7.1C.01231.A8C42905; Thu, 01 Nov 2012 19:18:50 +0900 (KST) Received: from DOJG1HAN02 ([12.23.120.99]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MCT0084B0NDEPE0@mmp2.samsung.com> for linux-fbdev@vger.kernel.org; Thu, 01 Nov 2012 19:18:50 +0900 (KST) From: Jingoo Han To: 'Florian Tobias Schandinat' Cc: linux-fbdev@vger.kernel.org, 'Sean Paul' , 'Jingoo Han' Subject: [PATCH v3 1/8] video: exynos_dp: Check DPCD return codes Date: Thu, 01 Nov 2012 19:18:49 +0900 Message-id: <011d01cdb81a$4914c1d0$db3e4570$%han@samsung.com> MIME-version: 1.0 Content-type: text/plain; charset=us-ascii Content-transfer-encoding: 7bit X-Mailer: Microsoft Office Outlook 12.0 Thread-index: Ac24Gkjta+Tb9VxGTiWIp02dvaPqfw== Content-language: ko X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrILMWRmVeSWpSXmKPExsVy+t9jQd0un0kBBk9/cFic6PvA6sDo8XmT XABjFJdNSmpOZllqkb5dAlfGgyUHWQtu2FV8eLCVrYFxkXEXIyeHhICJxPbOZ8wQtpjEhXvr 2boYuTiEBKYzStx7M5EVwpnFJLHj+i6wKjYBNYkvXw6zdzFycIgIWEls2qoJYjILZEmcPqYA UiEs4Chx/sUOVhCbRUBV4uneXWDVvAK2Et2rS0HCvAKCEj8m32MBsZkFtCTW7zzOBGHLS2xe 85YZpFxCQF3i0V9diD16EhfWp0FUiEjse/GOcQKjwCwkg2YhGTQLyaBZSFoWMLKsYhRNLUgu KE5KzzXUK07MLS7NS9dLzs/dxAgOyGdSOxhXNlgcYhTgYFTi4TUsnRggxJpYVlyZe4hRgoNZ SYT3cTdQiDclsbIqtSg/vqg0J7X4EKM0B4uSOG+zR0qAkEB6YklqdmpqQWoRTJaJg1OqgbHY JV12xUf1x7KPw95+ui8z7Zxk9qsNM+2ZS4zSrBxfOfKynxM2X1ARsDCh/dfS+Rnf2d6GO32V Zdiq8NLK7SHb3R3v2O9GxivbZUpZ+M9p+iy+KuDv6uppitE1XyfGff5ZcjJI8V5Gh07uYxXH 9Wt3B9qaPor9KGyttKcxRfu9us0Cn8ONn5RYijMSDbWYi4oTAZM75XREAgAA Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org From: Sean Paul Add return code checks to the DPCD transactions in the SW link training Signed-off-by: Sean Paul Signed-off-by: Jingoo Han --- drivers/video/exynos/exynos_dp_core.c | 86 +++++++++++++++++++++----------- 1 files changed, 56 insertions(+), 30 deletions(-) diff --git a/drivers/video/exynos/exynos_dp_core.c b/drivers/video/exynos/exynos_dp_core.c index d55470e..44820f2 100644 --- a/drivers/video/exynos/exynos_dp_core.c +++ b/drivers/video/exynos/exynos_dp_core.c @@ -261,11 +261,10 @@ static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp, } } -static void exynos_dp_link_start(struct exynos_dp_device *dp) +static int exynos_dp_link_start(struct exynos_dp_device *dp) { u8 buf[4]; - int lane; - int lane_count; + int lane, lane_count, retval; lane_count = dp->link_train.lane_count; @@ -276,8 +275,10 @@ static void exynos_dp_link_start(struct exynos_dp_device *dp) dp->link_train.cr_loop[lane] = 0; /* Set sink to D0 (Sink Not Ready) mode. */ - exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_SINK_POWER_STATE, + retval = exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_SINK_POWER_STATE, DPCD_SET_POWER_STATE_D0); + if (retval) + return retval; /* Set link rate and count as you want to establish*/ exynos_dp_set_link_bandwidth(dp, dp->link_train.link_rate); @@ -286,8 +287,10 @@ static void exynos_dp_link_start(struct exynos_dp_device *dp) /* Setup RX configuration */ buf[0] = dp->link_train.link_rate; buf[1] = dp->link_train.lane_count; - exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_LINK_BW_SET, + retval = exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_LINK_BW_SET, 2, buf); + if (retval) + return retval; /* Set TX pre-emphasis to minimum */ for (lane = 0; lane < lane_count; lane++) @@ -306,9 +309,11 @@ static void exynos_dp_link_start(struct exynos_dp_device *dp) for (lane = 0; lane < lane_count; lane++) buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 | DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0; - exynos_dp_write_bytes_to_dpcd(dp, + retval = exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_TRAINING_LANE0_SET, lane_count, buf); + + return retval; } static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane) @@ -430,8 +435,7 @@ static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp) static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp) { u8 link_status[2]; - int lane; - int lane_count; + int lane, lane_count, retval; u8 adjust_request[2]; u8 voltage_swing; @@ -442,17 +446,22 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp) lane_count = dp->link_train.lane_count; - exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS, + retval = exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS, 2, link_status); + if (retval) + return retval; if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) { /* set training pattern 2 for EQ */ exynos_dp_set_training_pattern(dp, TRAINING_PTN2); for (lane = 0; lane < lane_count; lane++) { - exynos_dp_read_bytes_from_dpcd(dp, + retval = exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_ADJUST_REQUEST_LANE0_1, 2, adjust_request); + if (retval) + return retval; + voltage_swing = exynos_dp_get_adjust_request_voltage( adjust_request, lane); pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis( @@ -472,15 +481,19 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp) lane); } - exynos_dp_write_byte_to_dpcd(dp, + retval = exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_TRAINING_PATTERN_SET, DPCD_SCRAMBLING_DISABLED | DPCD_TRAINING_PATTERN_2); + if (retval) + return retval; - exynos_dp_write_bytes_to_dpcd(dp, + retval = exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_TRAINING_LANE0_SET, lane_count, dp->link_train.training_lane); + if (retval) + return retval; dev_info(dp->dev, "Link Training Clock Recovery success\n"); dp->link_train.lt_state = EQUALIZER_TRAINING; @@ -488,9 +501,12 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp) for (lane = 0; lane < lane_count; lane++) { training_lane = exynos_dp_get_lane_link_training( dp, lane); - exynos_dp_read_bytes_from_dpcd(dp, + retval = exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_ADJUST_REQUEST_LANE0_1, 2, adjust_request); + if (retval) + return retval; + voltage_swing = exynos_dp_get_adjust_request_voltage( adjust_request, lane); pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis( @@ -527,13 +543,14 @@ static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp) dp->link_train.training_lane[lane], lane); } - exynos_dp_write_bytes_to_dpcd(dp, - DPCD_ADDR_TRAINING_LANE0_SET, - lane_count, - dp->link_train.training_lane); + retval = exynos_dp_write_bytes_to_dpcd(dp, + DPCD_ADDR_TRAINING_LANE0_SET, lane_count, + dp->link_train.training_lane); + if (retval) + return retval; } - return 0; + return retval; reduce_link_rate: exynos_dp_reduce_link_rate(dp); @@ -544,8 +561,7 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp) { u8 link_status[2]; u8 link_align[3]; - int lane; - int lane_count; + int lane, lane_count, retval; u32 reg; u8 adjust_request[2]; @@ -557,8 +573,10 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp) lane_count = dp->link_train.lane_count; - exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS, + retval = exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS, 2, link_status); + if (retval) + return retval; if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) { link_align[0] = link_status[0]; @@ -569,9 +587,12 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp) &link_align[2]); for (lane = 0; lane < lane_count; lane++) { - exynos_dp_read_bytes_from_dpcd(dp, + retval = exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_ADJUST_REQUEST_LANE0_1, 2, adjust_request); + if (retval) + return retval; + voltage_swing = exynos_dp_get_adjust_request_voltage( adjust_request, lane); pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis( @@ -620,10 +641,12 @@ static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp) dp->link_train.training_lane[lane], lane); - exynos_dp_write_bytes_to_dpcd(dp, - DPCD_ADDR_TRAINING_LANE0_SET, - lane_count, - dp->link_train.training_lane); + retval = exynos_dp_write_bytes_to_dpcd(dp, + DPCD_ADDR_TRAINING_LANE0_SET, + lane_count, + dp->link_train.training_lane); + if (retval) + return retval; } } else { goto reduce_link_rate; @@ -701,16 +724,17 @@ static void exynos_dp_init_training(struct exynos_dp_device *dp, static int exynos_dp_sw_link_training(struct exynos_dp_device *dp) { - int retval = 0; - int training_finished = 0; + int retval = 0, training_finished = 0; dp->link_train.lt_state = START; /* Process here */ - while (!training_finished) { + while (!retval && !training_finished) { switch (dp->link_train.lt_state) { case START: - exynos_dp_link_start(dp); + retval = exynos_dp_link_start(dp); + if (retval) + dev_err(dp->dev, "LT link start failed!\n"); break; case CLOCK_RECOVERY: retval = exynos_dp_process_clock_recovery(dp); @@ -729,6 +753,8 @@ static int exynos_dp_sw_link_training(struct exynos_dp_device *dp) return -EREMOTEIO; } } + if (retval) + dev_err(dp->dev, "eDP link training failed (%d)\n", retval); return retval; }