From patchwork Thu Nov 1 10:21:08 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jingoo Han X-Patchwork-Id: 1684231 Return-Path: X-Original-To: patchwork-linux-fbdev@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id B0E34E003B for ; Thu, 1 Nov 2012 10:21:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758026Ab2KAKVL (ORCPT ); Thu, 1 Nov 2012 06:21:11 -0400 Received: from mailout1.samsung.com ([203.254.224.24]:22498 "EHLO mailout1.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757363Ab2KAKVK (ORCPT ); Thu, 1 Nov 2012 06:21:10 -0400 Received: from epcpsbgm2.samsung.com (epcpsbgm2 [203.254.230.27]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MCT0081M0R5LKT0@mailout1.samsung.com> for linux-fbdev@vger.kernel.org; Thu, 01 Nov 2012 19:21:09 +0900 (KST) X-AuditID: cbfee61b-b7f616d00000319b-cf-50924d14aba3 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 68.C9.12699.41D42905; Thu, 01 Nov 2012 19:21:09 +0900 (KST) Received: from DOJG1HAN02 ([12.23.120.99]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MCT0093S0R8P920@mmp2.samsung.com> for linux-fbdev@vger.kernel.org; Thu, 01 Nov 2012 19:21:08 +0900 (KST) From: Jingoo Han To: 'Florian Tobias Schandinat' Cc: linux-fbdev@vger.kernel.org, 'Sean Paul' , 'Jingoo Han' References: <011d01cdb81a$4914c1d0$db3e4570$%han@samsung.com> In-reply-to: <011d01cdb81a$4914c1d0$db3e4570$%han@samsung.com> Subject: [PATCH v3 3/8] video: exynos_dp: Get pll lock before pattern set Date: Thu, 01 Nov 2012 19:21:08 +0900 Message-id: <011f01cdb81a$9bf1fbc0$d3d5f340$%han@samsung.com> MIME-version: 1.0 Content-type: text/plain; charset=us-ascii Content-transfer-encoding: 7bit X-Mailer: Microsoft Office Outlook 12.0 Thread-index: Ac24Gkjta+Tb9VxGTiWIp02dvaPqfwAACe4g Content-language: ko X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrFLMWRmVeSWpSXmKPExsVy+t9jQV1R30kBBmsXsVic6PvA6sDo8XmT XABjFJdNSmpOZllqkb5dAlfGl4O3GQueclc0npVuYHzL2cXIySEhYCIx9XADG4QtJnHh3nog m4tDSGA6o8Svm49ZIJxZTBLrpzYxg1SxCahJfPlymL2LkYNDRMBKYtNWTRCTWSBL4vQxBZAK IQFbiXUtnxhBbE4BO4nWh01MILawgKfEsVMHwWwWAVWJF49Og+3lBaqfvLeBEcIWlPgx+R4L iM0soCWxfudxJghbXmLzmrfMIKskBNQlHv3VBQmLCBhJ3Dv/hQ2iRERi34t3jBMYhWYhmTQL yaRZSCbNQtKygJFlFaNoakFyQXFSeq6RXnFibnFpXrpecn7uJkZwCD+T3sG4qsHiEKMAB6MS D++EuokBQqyJZcWVuYcYJTiYlUR4H3cDhXhTEiurUovy44tKc1KLDzFKc7AoifM2e6QECAmk J5akZqemFqQWwWSZODilGhil4irVHgpef1IuZzNx5S0z7fP1ijmeEgtOPn97cp7PHaaTs0+X TjMUDVBSinFl0I/vyf9mOC3TVX9p7fNvO/cf7Ut6EPnQyl9+wa3vH8syZbp3/VLpC60Rn9+V 6pK694cwe9eKijX11f5z7gnrbzpV8yr2UkOkY9qv7/9WFMy5Nj+N40Vmp5sSS3FGoqEWc1Fx IgD63TmgXQIAAA== Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org From: Sean Paul According to the exynos datasheet (Figure 49-10), we should wait for PLL lock before programming the training pattern when doing software eDP link training. Signed-off-by: Sean Paul Signed-off-by: Jingoo Han --- drivers/video/exynos/exynos_dp_core.c | 14 +++++++++++++- 1 files changed, 13 insertions(+), 1 deletions(-) diff --git a/drivers/video/exynos/exynos_dp_core.c b/drivers/video/exynos/exynos_dp_core.c index 13bb10d..878b4b6 100644 --- a/drivers/video/exynos/exynos_dp_core.c +++ b/drivers/video/exynos/exynos_dp_core.c @@ -264,7 +264,7 @@ static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp, static int exynos_dp_link_start(struct exynos_dp_device *dp) { u8 buf[4]; - int lane, lane_count, retval; + int lane, lane_count, pll_tries, retval; lane_count = dp->link_train.lane_count; @@ -297,6 +297,18 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp) exynos_dp_set_lane_lane_pre_emphasis(dp, PRE_EMPHASIS_LEVEL_0, lane); + /* Wait for PLL lock */ + pll_tries = 0; + while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { + if (pll_tries == DP_TIMEOUT_LOOP_COUNT) { + dev_err(dp->dev, "Wait for PLL lock timed out\n"); + return -ETIMEDOUT; + } + + pll_tries++; + usleep_range(90, 120); + } + /* Set training pattern 1 */ exynos_dp_set_training_pattern(dp, TRAINING_PTN1);