From patchwork Wed Oct 17 11:20:28 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 1605091 Return-Path: X-Original-To: patchwork-linux-fbdev@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id A020F3FE36 for ; Wed, 17 Oct 2012 11:20:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756255Ab2JQLUp (ORCPT ); Wed, 17 Oct 2012 07:20:45 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:59174 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755626Ab2JQLUn (ORCPT ); Wed, 17 Oct 2012 07:20:43 -0400 Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id q9HBKgvm009870; Wed, 17 Oct 2012 06:20:42 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id q9HBKgxg031457; Wed, 17 Oct 2012 06:20:42 -0500 Received: from dlelxv22.itg.ti.com (172.17.1.197) by dfle72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.1.323.3; Wed, 17 Oct 2012 06:20:42 -0500 Received: from deskari.tieu.ti.com (h64-2.vpn.ti.com [172.24.64.2]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id q9HBKbNf030439; Wed, 17 Oct 2012 06:20:41 -0500 From: Tomi Valkeinen To: , , CC: Tomi Valkeinen Subject: [PATCH 2/9] OMAPDSS: fix registering the vsync isr in apply Date: Wed, 17 Oct 2012 14:20:28 +0300 Message-ID: <1350472835-28727-3-git-send-email-tomi.valkeinen@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1350472835-28727-1-git-send-email-tomi.valkeinen@ti.com> References: <1350472835-28727-1-git-send-email-tomi.valkeinen@ti.com> MIME-Version: 1.0 Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org When we enable an output we don't check if we need to register the vsync isr. This causes us to miss vsync interrupts until somebody changes the configuration of an overlay or an overlay manager. Add the registration to dss_mgr_enable to fix the problem. Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/apply.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/video/omap2/dss/apply.c b/drivers/video/omap2/dss/apply.c index 19d66f4..29ce5a8 100644 --- a/drivers/video/omap2/dss/apply.c +++ b/drivers/video/omap2/dss/apply.c @@ -1035,6 +1035,9 @@ int dss_mgr_enable(struct omap_overlay_manager *mgr) if (!mgr_manual_update(mgr)) mp->updating = true; + if (!dss_data.irq_enabled && need_isr()) + dss_register_vsync_isr(); + spin_unlock_irqrestore(&data_lock, flags); if (!mgr_manual_update(mgr))