From patchwork Wed Oct 31 17:01:57 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Paul X-Patchwork-Id: 1680421 Return-Path: X-Original-To: patchwork-linux-fbdev@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id F2FE73FDDA for ; Wed, 31 Oct 2012 17:02:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752503Ab2JaRCF (ORCPT ); Wed, 31 Oct 2012 13:02:05 -0400 Received: from mail-qc0-f174.google.com ([209.85.216.174]:65219 "EHLO mail-qc0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751956Ab2JaRCE (ORCPT ); Wed, 31 Oct 2012 13:02:04 -0400 Received: by mail-qc0-f174.google.com with SMTP id o22so1100847qcr.19 for ; Wed, 31 Oct 2012 10:02:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=rhDAcp/sWzL2dXPleSGGR1WrI/K3i+J6qDrniFfyvSM=; b=kAtHPAk5uEn52Qhaq6WKFa+ycWItnDWAZgNtQnase2bJ+ZdiXX8prFN/zPYQ6mQRMc +YVZnrZACqo8tKdfR7WvG+jG/2M2wsuTf95p62IDFRi+MjRD66sB5nzOvb5kIcQxd2/H +H5pZaWkDixs4m05CKw9VXaa/gLZx3EPZLNYg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=rhDAcp/sWzL2dXPleSGGR1WrI/K3i+J6qDrniFfyvSM=; b=SfuzupEhQippzK6KiSKTmhKz5eJ9ihyVGBc2zFh078/dP+JdKTCLqBh8YgZFTABFGY hm+HthXwu5R8CAljyTqI0dhdia8bmQySlGIdM/bD6e5T96P3aqYt/6xDZ74OHdwGfFiw NkhmGuyK2DwFWdd0oBEaiRyBvYCxNztC2JvtrnlMNFE81DstCK2FiTwsP19//Eti7VFc sQ88mDIIXbwvGGZ/AdDUr7TG2eYNk1xaWEygUtejgYtcS+OGBUYKLjntbuJZ10IsrN3g Ku9y/RKnFv+kx9e014YhK67EU90bG6wuI8Cgj7TNaRVGqom+UVIvtYHOY696AJLx5mUW YPJQ== Received: by 10.224.188.76 with SMTP id cz12mr19152208qab.6.1351702923522; Wed, 31 Oct 2012 10:02:03 -0700 (PDT) Received: from seanpaul-linux2.cnc.corp.google.com (seanpaul-linux2.cnc.corp.google.com [172.29.92.76]) by mx.google.com with ESMTPS id g9sm1988388qaj.18.2012.10.31.10.02.02 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 31 Oct 2012 10:02:03 -0700 (PDT) From: Sean Paul To: jg1.han@samsung.com, FlorianSchandinat@gmx.de, linux-fbdev@vger.kernel.org Cc: Sean Paul Subject: [PATCH] video: exynos_dp: Get pll lock before pattern set Date: Wed, 31 Oct 2012 13:01:57 -0400 Message-Id: <1351702917-1331-1-git-send-email-seanpaul@chromium.org> X-Mailer: git-send-email 1.7.7.3 In-Reply-To: <004a01cd7eb4$04ce1480$0e6a3d80$%han@samsung.com> References: <004a01cd7eb4$04ce1480$0e6a3d80$%han@samsung.com> X-Gm-Message-State: ALoCoQkhocfG3kiWX5+lZe6L6bsECWb9E6gVJICms5r1RjfOVi24hw5Vr+/gZFYT0zz3sh/mZDqV Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org According to the exynos datasheet (Figure 49-10), we should wait for PLL lock before programming the training pattern when doing software eDP link training. Signed-off-by: Sean Paul --- drivers/video/exynos/exynos_dp_core.c | 14 +++++++++++++- 1 files changed, 13 insertions(+), 1 deletions(-) diff --git a/drivers/video/exynos/exynos_dp_core.c b/drivers/video/exynos/exynos_dp_core.c index b126e8a..ef9b003 100644 --- a/drivers/video/exynos/exynos_dp_core.c +++ b/drivers/video/exynos/exynos_dp_core.c @@ -264,7 +264,7 @@ static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp, static int exynos_dp_link_start(struct exynos_dp_device *dp) { u8 buf[4]; - int lane, lane_count, retval; + int lane, lane_count, pll_tries, retval; lane_count = dp->link_train.lane_count; @@ -297,6 +297,18 @@ static int exynos_dp_link_start(struct exynos_dp_device *dp) exynos_dp_set_lane_lane_pre_emphasis(dp, PRE_EMPHASIS_LEVEL_0, lane); + /* Wait for PLL lock */ + pll_tries = 0; + while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { + if (pll_tries == DP_TIMEOUT_LOOP_COUNT) { + dev_err(dp->dev, "Wait for PLL lock timed out\n"); + return -ETIMEDOUT; + } + + pll_tries++; + usleep_range(90, 120); + } + /* Set training pattern 1 */ exynos_dp_set_training_pattern(dp, TRAINING_PTN1);