From patchwork Thu Nov 15 15:58:15 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 1750111 Return-Path: X-Original-To: patchwork-linux-fbdev@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 3397DDF2AB for ; Thu, 15 Nov 2012 15:59:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933341Ab2KOP7V (ORCPT ); Thu, 15 Nov 2012 10:59:21 -0500 Received: from arroyo.ext.ti.com ([192.94.94.40]:52165 "EHLO arroyo.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933340Ab2KOP7U (ORCPT ); Thu, 15 Nov 2012 10:59:20 -0500 Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id qAFFxKMB003775; Thu, 15 Nov 2012 09:59:20 -0600 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id qAFFxKb2029656; Thu, 15 Nov 2012 09:59:20 -0600 Received: from dlelxv22.itg.ti.com (172.17.1.197) by dfle72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.1.323.3; Thu, 15 Nov 2012 09:59:19 -0600 Received: from deskari.tieu.ti.com (h68-10.vpn.ti.com [172.24.68.10]) by dlelxv22.itg.ti.com (8.13.8/8.13.8) with ESMTP id qAFFx6v4025421; Thu, 15 Nov 2012 09:59:18 -0600 From: Tomi Valkeinen To: Archit Taneja , Rob Clark CC: , , Tomi Valkeinen Subject: [PATCH 07/32] OMAPDSS: cleanup WB enable/is_enabled functions Date: Thu, 15 Nov 2012 17:58:15 +0200 Message-ID: <1352995120-3288-8-git-send-email-tomi.valkeinen@ti.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1352995120-3288-1-git-send-email-tomi.valkeinen@ti.com> References: <1352995120-3288-1-git-send-email-tomi.valkeinen@ti.com> MIME-Version: 1.0 Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org Instead of doing direct register reads/writes, dispc_wb_enable() and dispc_wb_is_enabled() functions can use the common overlay functions to set and check the enable bit. Signed-off-by: Tomi Valkeinen --- drivers/video/omap2/dss/dispc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c index 0dca3ff..662bf56 100644 --- a/drivers/video/omap2/dss/dispc.c +++ b/drivers/video/omap2/dss/dispc.c @@ -2804,12 +2804,12 @@ void dispc_mgr_disable_sync(enum omap_channel channel) void dispc_wb_enable(bool enable) { - REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(OMAP_DSS_WB), enable ? 1 : 0, 0, 0); + dispc_ovl_enable(OMAP_DSS_WB, enable); } bool dispc_wb_is_enabled(void) { - return REG_GET(DISPC_OVL_ATTRIBUTES(OMAP_DSS_WB), 0, 0); + return dispc_ovl_enabled(OMAP_DSS_WB); } static void dispc_lcd_enable_signal_polarity(bool act_high)