From patchwork Tue Mar 26 13:45:25 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: archit taneja X-Patchwork-Id: 2337211 Return-Path: X-Original-To: patchwork-linux-fbdev@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id 878D73FD40 for ; Tue, 26 Mar 2013 13:46:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934449Ab3CZNqw (ORCPT ); Tue, 26 Mar 2013 09:46:52 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:36863 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934428Ab3CZNqv (ORCPT ); Tue, 26 Mar 2013 09:46:51 -0400 Received: from dlelxv30.itg.ti.com ([172.17.2.17]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id r2QDknFw012812; Tue, 26 Mar 2013 08:46:49 -0500 Received: from DFLE73.ent.ti.com (dfle73.ent.ti.com [128.247.5.110]) by dlelxv30.itg.ti.com (8.13.8/8.13.8) with ESMTP id r2QDknkA029580; Tue, 26 Mar 2013 08:46:49 -0500 Received: from dlelxv24.itg.ti.com (172.17.1.199) by DFLE73.ent.ti.com (128.247.5.110) with Microsoft SMTP Server id 14.2.342.3; Tue, 26 Mar 2013 08:46:49 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dlelxv24.itg.ti.com (8.13.8/8.13.8) with ESMTP id r2QDkn7u017554; Tue, 26 Mar 2013 08:46:49 -0500 Received: from localhost (a0393947pc.apr.dhcp.ti.com [172.24.136.59]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id r2QDkkV13774; Tue, 26 Mar 2013 08:46:47 -0500 (CDT) From: Archit Taneja To: , , CC: , , , Archit Taneja Subject: [PATCH v2 8/8] OMAPDSS: DISPC: Revert to older DISPC Smart Standby mechanism for OMAP5 Date: Tue, 26 Mar 2013 19:15:25 +0530 Message-ID: <1364305525-28496-9-git-send-email-archit@ti.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1364305525-28496-1-git-send-email-archit@ti.com> References: <1362493070-17706-1-git-send-email-archit@ti.com> <1364305525-28496-1-git-send-email-archit@ti.com> MIME-Version: 1.0 Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org DISPC on OMAP5 has a more optimised mechanism of asserting Mstandby to achieve more power savings when DISPC is configured in Smart Standby mode. This mechanism leads to underflows when multiple DISPC pipes are enabled. There is a register field which can let us revert to the older mechanism of asserting Mstandby. Configure this field to prevent underflows. Signed-off-by: Archit Taneja --- drivers/video/omap2/dss/dispc.c | 7 +++++++ drivers/video/omap2/dss/dispc.h | 1 + 2 files changed, 8 insertions(+) diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c index ddbf031..b33b016 100644 --- a/drivers/video/omap2/dss/dispc.c +++ b/drivers/video/omap2/dss/dispc.c @@ -87,6 +87,9 @@ struct dispc_features { /* no DISPC_IRQ_FRAMEDONETV on this SoC */ bool no_framedone_tv:1; + + /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */ + bool mstandby_workaround:1; }; #define DISPC_MAX_NR_FIFOS 5 @@ -3502,6 +3505,9 @@ static void _omap_dispc_initial_config(void) dispc_configure_burst_sizes(); dispc_ovl_enable_zorder_planes(); + + if (dispc.feat->mstandby_workaround) + REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0); } static const struct dispc_features omap24xx_dispc_feats __initconst = { @@ -3596,6 +3602,7 @@ static const struct dispc_features omap54xx_dispc_feats __initconst = { .calc_core_clk = calc_core_clk_44xx, .num_fifos = 5, .gfx_fifo_workaround = true, + .mstandby_workaround = true, }; static int __init dispc_init_features(struct platform_device *pdev) diff --git a/drivers/video/omap2/dss/dispc.h b/drivers/video/omap2/dss/dispc.h index 222363c..de4863d 100644 --- a/drivers/video/omap2/dss/dispc.h +++ b/drivers/video/omap2/dss/dispc.h @@ -39,6 +39,7 @@ #define DISPC_GLOBAL_BUFFER 0x0800 #define DISPC_CONTROL3 0x0848 #define DISPC_CONFIG3 0x084C +#define DISPC_MSTANDBY_CTRL 0x0858 /* DISPC overlay registers */ #define DISPC_OVL_BA0(n) (DISPC_OVL_BASE(n) + \