From patchwork Mon Sep 16 17:18:53 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pawel Moll X-Patchwork-Id: 2898801 Return-Path: X-Original-To: patchwork-linux-fbdev@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 5734E9F1C0 for ; Mon, 16 Sep 2013 17:19:11 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id DBF002015A for ; Mon, 16 Sep 2013 17:19:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6BAC420257 for ; Mon, 16 Sep 2013 17:19:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751347Ab3IPRTE (ORCPT ); Mon, 16 Sep 2013 13:19:04 -0400 Received: from service87.mimecast.com ([91.220.42.44]:44506 "EHLO service87.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751197Ab3IPRTC (ORCPT ); Mon, 16 Sep 2013 13:19:02 -0400 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Mon, 16 Sep 2013 18:18:58 +0100 Received: from hornet.cambridge.arm.com ([10.1.255.212]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 16 Sep 2013 18:18:57 +0100 From: Pawel Moll To: linux-fbdev@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Rob Herring , Mark Rutland , Stephen Warren , Ian Campbell , Jean-Christophe Plagniol-Villard , Tomi Valkeinen , Russell King , Arnd Bergmann , Sylwester Nawrocki , Pawel Moll Subject: [PATCH v3 1/2] video: ARM CLCD: Add DT support Date: Mon, 16 Sep 2013 18:18:53 +0100 Message-Id: <1379351934-25415-1-git-send-email-pawel.moll@arm.com> X-Mailer: git-send-email 1.8.1.2 X-OriginalArrivalTime: 16 Sep 2013 17:18:57.0735 (UTC) FILETIME=[D3EEFD70:01CEB300] X-MC-Unique: 113091618185801501 Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org X-Spam-Status: No, score=-4.0 required=5.0 tests=BAYES_00,KHOP_BIG_TO_CC, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds basic DT bindings for the PL11x CLCD controllers and make their fbdev driver use them (initially only TFT panels are supported). Signed-off-by: Pawel Moll --- Changes since v2: - replaced video-ram phandle with arm,pl11x,framebuffer-base - replaced panel-* properties with arm,pl11x,panel-data-pads - replaced max-framebuffer-size with max-memory-bandwidth - modified clcdfb_of_init_tft_panel() to use the pads data and take differences between PL110 and PL110 into account Changes since v1: - minor code cleanups as suggested by Sylwester Nawrocki .../devicetree/bindings/video/arm,pl11x.txt | 145 +++++++++++ drivers/video/Kconfig | 1 + drivers/video/amba-clcd.c | 268 +++++++++++++++++++++ 3 files changed, 414 insertions(+) create mode 100644 Documentation/devicetree/bindings/video/arm,pl11x.txt diff --git a/Documentation/devicetree/bindings/video/arm,pl11x.txt b/Documentation/devicetree/bindings/video/arm,pl11x.txt new file mode 100644 index 0000000..418ee06 --- /dev/null +++ b/Documentation/devicetree/bindings/video/arm,pl11x.txt @@ -0,0 +1,145 @@ +* ARM PrimeCell Color LCD Controller PL110/PL111 + +See also Documentation/devicetree/bindings/arm/primecell.txt + +Required properties: + +- compatible: must be one of: + "arm,pl110", "arm,primecell" + "arm,pl111", "arm,primecell" +- reg: base address and size of the control registers block +- interrupts: either a single interrupt specifier representing the + combined interrupt output (CLCDINTR) or an array of + four interrupt specifiers for CLCDMBEINTR, + CLCDVCOMPINTR, CLCDLNBUINTR, CLCDFUFINTR; in the + latter case interrupt names must be specified + (see below) +- interrupt-names: when four interrupts are specified, their names: + "mbe", "vcomp", "lnbu", "fuf" + must be specified in order respective to the + interrupt specifiers +- clocks: contains phandle and clock specifier pairs for the entries + in the clock-names property. See + Documentation/devicetree/binding/clock/clock-bindings.txt +- clocks names: should contain "clcdclk" and "apb_pclk" +- arm,pl11x,panel-data-pads: array of 24 cells, each of them describing + a function of one of the CLD pads, + starting from 0 up to 23; each pad can + be described by one of the following values: + - 0: reserved (not connected) + - 0x100-0x107: color upper STN panel data 0 to 7 + - 0x110-0x117: color lower STN panel data 0 to 7 + - 0x200-0x207: mono upper STN panel data 0 to 7 + - 0x210-0x217: mono lower STN panel data 0 to 7 + - 0x300-0x307: red component bit 0 to 7 of TFT panel data + - 0x310-0x317: green component bit 0 to 7 of TFT panel data + - 0x320-0x327: blue component bit 0 to 7 of TFT panel data + - 0x330: intensity bit of TFT panel data + Example sets of values for standard + panel interfaces: + - PL110 single colour STN panel: + <0x107 0x106 0x105 0x104 0x103 0x102 0x101 0x100>, + <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; + - PL110 dual colour STN panel: + <0x107 0x106 0x105 0x104 0x103 0x102 0x101 0x100>, + <0x117 0x116 0x115 0x114 0x113 0x112 0x111 0x110>, + <0 0 0 0 0 0 0 0>; + - PL110 single mono 4-bit STN panel: + <0x203 0x202 0x201 0x200>, + <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; + - PL110 dual mono 4-bit STN panel: + <0x203 0x202 0x201 0x200>, <0 0 0 0>, + <0x213 0x212 0x211 0x210>, + <0 0 0 0 0 0 0 0 0 0 0 0>; + - PL110 single mono 8-bit STN panel: + <0x207 0x206 0x205 0x204 0x203 0x202 0x201 0x200>, + <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; + - PL110 dual mono 8-bit STN panel: + <0x207 0x206 0x205 0x204 0x203 0x202 0x201 0x200>, + <0x217 0x216 0x215 0x214 0x213 0x212 0x211 0x210>, + <0 0 0 0 0 0 0 0>; + - PL110 TFT (1:)5:5:5 panel: + <0x330 0x300 0x301 0x302 0x303 0x304>, + <0x330 0x310 0x311 0x312 0x313 0x314>, + <0x330 0x320 0x321 0x322 0x323 0x324>, + <0 0 0 0 0 0> + - PL110 and PL111 TFT RGB 888 panel: + <0x300 0x301 0x302 0x303 0x304 0x305 0x306 0x307>, + <0x310 0x311 0x312 0x313 0x314 0x315 0x316 0x317>, + <0x320 0x321 0x322 0x323 0x324 0x325 0x326 0x327>; + - PL111 single colour STN panel: + <0x100 0x101 0x102 0x103 0x104 0x105 0x106 0x107>, + <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; + - PL111 dual colour STN panel: + <0x100 0x101 0x102 0x103 0x104 0x105 0x106 0x107>, + <0x110 0x111 0x112 0x113 0x114 0x115 0x116 0x117>, + <0 0 0 0 0 0 0 0>; + - PL111 single mono 4-bit STN panel: + <0x200 0x201 0x202 0x203>, + <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; + - PL111 dual mono 4-bit STN panel: + <0x200 0x201 0x202 0x203>, <0 0 0 0>, + <0x210 0x211 0x212 0x213>, + <0 0 0 0 0 0 0 0 0 0 0 0>; + - PL111 single mono 8-bit STN panel: + <0x200 0x201 0x202 0x203 0x204 0x205 0x206 0x207>, + <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; + - PL111 dual mono 8-bit STN panel: + <0x200 0x201 0x202 0x203 0x204 0x205 0x206 0x207>, + <0x210 0x211 0x212 0x213 0x214 0x215 0x216 0x217>, + <0 0 0 0 0 0 0 0>; + - PL111 TFT 4:4:4 panel: + <0 0 0 0>, <0x300 0x301 0x302 0x303>, + <0 0 0 0>, <0x310 0x311 0x312 0x313>, + <0 0 0 0>, <0x320 0x321 0x322 0x323>; + - PL111 TFT 5:6:5 panel: + <0 0 0>, <0x300 0x301 0x302 0x303 0x304>, + <0 0>, <0x310 0x311 0x312 0x313 0x314 0x315>, + <0 0 0>, <0x320 0x321 0x322 0x323 0x324>; + - PL111 TFT (1):5:5:5 panel: + <0 0 0>, <0x300 0x301 0x302 0x303 0x304>, + <0 0>, <0x330 0x310 0x311 0x312 0x313 0x314>, + <0 0 0>, <0x320 0x321 0x322 0x323 0x324>; + +Optional properties: + +- arm,pl11x,framebuffer-base: a pair of two values, address and size, + defining the framebuffer to be used; + to be used only if it is *not* + part of normal memory, as described + in /memory node +- max-memory-bandwidth: maximum bandwidth in bytes per second that the + cell's memory interface can handle +- display-timings: standard display timings sub-node, defining possible + video modes of a connected panel; for details see + Documentation/devicetree/bindings/video/display-timing.txt + +Example: + + clcd@1f0000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x1f0000 0x1000>; + interrupts = <14>; + clocks = <&v2m_oscclk1>, <&smbclk>; + clock-names = "clcdclk", "apb_pclk"; + + arm,pl11x,panel-data-pads = <0x300 0x301 0x302 0x303 0x304 0x305 0x306 0x307>, + <0x310 0x311 0x312 0x313 0x314 0x315 0x316 0x317>, + <0x320 0x321 0x322 0x323 0x324 0x325 0x326 0x327>; + arm,pl11x,framebuffer-base = <0x18000000 0x00800000>; + max-memory-bandwidth = <36864000>; /* bps, 640x480@60 16bpp */ + display-timings { + native-mode = <&v2m_clcd_timing0>; + v2m_clcd_timing0: vga { + clock-frequency = <25175000>; + hactive = <640>; + hback-porch = <40>; + hfront-porch = <24>; + hsync-len = <96>; + vactive = <480>; + vback-porch = <32>; + vfront-porch = <11>; + vsync-len = <2>; + }; + }; + }; diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 4cf1e1d..375bf63 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -316,6 +316,7 @@ config FB_ARMCLCD select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT + select VIDEOMODE_HELPERS if OF help This framebuffer device driver is for the ARM PrimeCell PL110 Colour LCD controller. ARM PrimeCells provide the building diff --git a/drivers/video/amba-clcd.c b/drivers/video/amba-clcd.c index 0a2cce7..03420d1 100644 --- a/drivers/video/amba-clcd.c +++ b/drivers/video/amba-clcd.c @@ -25,6 +25,11 @@ #include #include #include +#include +#include +#include +#include