From patchwork Wed Feb 26 09:59:59 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Denis Carikli X-Patchwork-Id: 3722881 Return-Path: X-Original-To: patchwork-linux-fbdev@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 2B5289F2F7 for ; Wed, 26 Feb 2014 10:00:37 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 108D22018E for ; Wed, 26 Feb 2014 10:00:36 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D6BB5201CD for ; Wed, 26 Feb 2014 10:00:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751839AbaBZKAa (ORCPT ); Wed, 26 Feb 2014 05:00:30 -0500 Received: from smtp6-g21.free.fr ([212.27.42.6]:60347 "EHLO smtp6-g21.free.fr" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751817AbaBZKA1 (ORCPT ); Wed, 26 Feb 2014 05:00:27 -0500 Received: from denis-N73SV.local.eukrea.com (unknown [88.170.243.169]) by smtp6-g21.free.fr (Postfix) with ESMTP id C4AE7822A0; Wed, 26 Feb 2014 11:00:20 +0100 (CET) From: Denis Carikli To: linux-arm-kernel@lists.infradead.org, linux-fbdev@vger.kernel.org Cc: Denis Carikli , =?UTF-8?q?Eric=20B=C3=A9nard?= , Shawn Guo Subject: [PATCHv6][ 5/5] ARM: dts: mbimxsd35 Add video and displays support. Date: Wed, 26 Feb 2014 10:59:59 +0100 Message-Id: <1393408800-8946-5-git-send-email-denis@eukrea.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1393408800-8946-1-git-send-email-denis@eukrea.com> References: <1393408800-8946-1-git-send-email-denis@eukrea.com> MIME-Version: 1.0 Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Cc: Eric Bénard Cc: Shawn Guo Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Denis Carikli --- ChangeLog v5->v6: - Shrinked the Cc list. - Added the targets in the Makefile - rebased not to use the now gone pingrp headers. ChangeLog v4->v5: - Added Grant Likely and Shawn Guo in the Cc list. - Adapted to the new non-dma ipu bindings. ChangeLog v3->v4: - Shortened the licenses. - adapted the dts(i) to the new bindings. ChangeLog v2->v3: - The dts were adapted to the new DT bindings which looks more like the IPUv3 ones. --- arch/arm/boot/dts/Makefile | 3 + arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi | 28 ++++++++++ .../imx35-eukrea-mbimxsd35-baseboard-cmo-qvga.dts | 58 ++++++++++++++++++++ .../imx35-eukrea-mbimxsd35-baseboard-dvi-svga.dts | 47 ++++++++++++++++ .../imx35-eukrea-mbimxsd35-baseboard-dvi-vga.dts | 47 ++++++++++++++++ 5 files changed, 183 insertions(+) create mode 100644 arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard-cmo-qvga.dts create mode 100644 arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard-dvi-svga.dts create mode 100644 arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard-dvi-vga.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index c98f343..ad0915e 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -167,6 +167,9 @@ dtb-$(CONFIG_ARCH_MXC) += \ imx27-phytec-phycard-s-rdk.dtb \ imx31-bug.dtb \ imx35-eukrea-mbimxsd35-baseboard.dtb \ + imx35-eukrea-mbimxsd35-baseboard-cmo-qvga.dtb \ + imx35-eukrea-mbimxsd35-baseboard-dvi-svga.dtb \ + imx35-eukrea-mbimxsd35-baseboard-dvi-vga.dtb \ imx50-evk.dtb \ imx51-apf51.dtb \ imx51-apf51dev.dtb \ diff --git a/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi b/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi index 906ae93..6596009 100644 --- a/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi +++ b/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi @@ -70,6 +70,34 @@ MX35_PAD_I2C1_DAT__I2C1_SDA 0x80000000 >; }; + + pinctrl_ipu_disp0: ipudisp0grp { + fsl,pins = < + MX35_PAD_LD0__IPU_DISPB_DAT_0 0x80000000 + MX35_PAD_LD1__IPU_DISPB_DAT_1 0x80000000 + MX35_PAD_LD2__IPU_DISPB_DAT_2 0x80000000 + MX35_PAD_LD3__IPU_DISPB_DAT_3 0x80000000 + MX35_PAD_LD4__IPU_DISPB_DAT_4 0x80000000 + MX35_PAD_LD5__IPU_DISPB_DAT_5 0x80000000 + MX35_PAD_LD6__IPU_DISPB_DAT_6 0x80000000 + MX35_PAD_LD7__IPU_DISPB_DAT_7 0x80000000 + MX35_PAD_LD8__IPU_DISPB_DAT_8 0x80000000 + MX35_PAD_LD9__IPU_DISPB_DAT_9 0x80000000 + MX35_PAD_LD10__IPU_DISPB_DAT_10 0x80000000 + MX35_PAD_LD11__IPU_DISPB_DAT_11 0x80000000 + MX35_PAD_LD12__IPU_DISPB_DAT_12 0x80000000 + MX35_PAD_LD13__IPU_DISPB_DAT_13 0x80000000 + MX35_PAD_LD14__IPU_DISPB_DAT_14 0x80000000 + MX35_PAD_LD15__IPU_DISPB_DAT_15 0x80000000 + MX35_PAD_LD16__IPU_DISPB_DAT_16 0x80000000 + MX35_PAD_LD17__IPU_DISPB_DAT_17 0x80000000 + MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC 0x80000000 + MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK 0x80000000 + MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY 0x80000000 + MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC 0x80000000 + MX35_PAD_CONTRAST__IPU_DISPB_CONTR 0x80000000 + >; + }; }; }; diff --git a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard-cmo-qvga.dts b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard-cmo-qvga.dts new file mode 100644 index 0000000..345f560 --- /dev/null +++ b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard-cmo-qvga.dts @@ -0,0 +1,58 @@ +/* + * Copyright 2013 Eukréa Electromatique + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx35-eukrea-mbimxsd35-baseboard.dts" + +/ { + model = "Eukrea MBIMXSD35 with the CMO-QVGA Display"; + compatible = "eukrea,mbimxsd35-baseboard-cmo-qvga", "eukrea,mbimxsd35-baseboard", "eukrea,cpuimx35", "fsl,imx35"; + + cmo_qvga: display@di0 { + compatible = "fsl,mx3-parallel-display"; + regulator-name = "lcd"; + interface-pix-fmt = "rgb666"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp0>; + lcd-supply = <®_lcd_3v3>; + model = "CMO-QVGA"; + display-timings { + qvga_timings: 320x240 { + clock-frequency = <6500000>; + hactive = <320>; + vactive = <240>; + hback-porch = <68>; + hfront-porch = <20>; + vback-porch = <15>; + vfront-porch = <4>; + hsync-len = <30>; + vsync-len = <3>; + }; + }; + }; + + reg_lcd_3v3: lcd-en { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_lcd_3v3>; + regulator-name = "lcd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 4 0>; + enable-active-high; + }; +}; + +&ipu { + display = <&cmo_qvga>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard-dvi-svga.dts b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard-dvi-svga.dts new file mode 100644 index 0000000..1a249d0 --- /dev/null +++ b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard-dvi-svga.dts @@ -0,0 +1,47 @@ +/* + * Copyright 2013 Eukréa Electromatique + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx35-eukrea-mbimxsd35-baseboard.dts" + +/ { + model = "Eukrea MBIMXSD35 with the DVI-SVGA Display"; + compatible = "eukrea,mbimxsd35-baseboard-dvi-svga", "eukrea,mbimxsd35-baseboard", "eukrea,cpuimx35", "fsl,imx35"; + dvi_svga: display@di0 { + interface-pix-fmt = "rgb666"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp0>; + model = "DVI-SVGA"; + display-timings { + svga_timings: 800x600 { + clock-frequency = <40000000>; + hactive = <800>; + vactive = <600>; + hback-porch = <75>; + hfront-porch = <75>; + vback-porch = <7>; + vfront-porch = <75>; + hsync-len = <7>; + vsync-len = <7>; + hsync-active = <1>; + vsync-active = <1>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&ipu { + display = <&dvi_svga>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard-dvi-vga.dts b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard-dvi-vga.dts new file mode 100644 index 0000000..44a7616 --- /dev/null +++ b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard-dvi-vga.dts @@ -0,0 +1,47 @@ +/* + * Copyright 2013 Eukréa Electromatique + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "imx35-eukrea-mbimxsd35-baseboard.dts" + +/ { + model = "Eukrea MBIMXSD35 with the DVI-VGA Display"; + compatible = "eukrea,mbimxsd35-baseboard-dvi-vga", "eukrea,mbimxsd35-baseboard", "eukrea,cpuimx35", "fsl,imx35"; + dvi_vga: display@di0 { + interface-pix-fmt = "rgb666"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp0>; + model = "DVI-VGA"; + display-timings { + vga_timings: 640x480 { + clock-frequency = <31250000>; + hactive = <640>; + vactive = <480>; + hback-porch = <100>; + hfront-porch = <100>; + vback-porch = <7>; + vfront-porch = <100>; + hsync-len = <7>; + vsync-len = <7>; + hsync-active = <1>; + vsync-active = <1>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&ipu { + display = <&dvi_vga>; + status = "okay"; +};