From patchwork Thu Apr 24 10:17:15 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 4047861 Return-Path: X-Original-To: patchwork-linux-fbdev@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 95BDE9F3E2 for ; Thu, 24 Apr 2014 10:19:35 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id D43722028D for ; Thu, 24 Apr 2014 10:19:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 063F32017D for ; Thu, 24 Apr 2014 10:19:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754532AbaDXKTa (ORCPT ); Thu, 24 Apr 2014 06:19:30 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:47179 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755149AbaDXKT1 (ORCPT ); Thu, 24 Apr 2014 06:19:27 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id s3OAJ7vO031760; Thu, 24 Apr 2014 05:19:07 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id s3OAJ7xH019666; Thu, 24 Apr 2014 05:19:07 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.174.1; Thu, 24 Apr 2014 05:19:07 -0500 Received: from deskari.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s3OAISm7009835; Thu, 24 Apr 2014 05:19:06 -0500 From: Tomi Valkeinen To: Archit Taneja , , , CC: Tomi Valkeinen Subject: [PATCH 19/23] OMAPDSS: HDMI: support larger register offsets for OMAP5 HDMI core Date: Thu, 24 Apr 2014 13:17:15 +0300 Message-ID: <1398334639-14172-20-git-send-email-tomi.valkeinen@ti.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1398334639-14172-1-git-send-email-tomi.valkeinen@ti.com> References: <1398334639-14172-1-git-send-email-tomi.valkeinen@ti.com> MIME-Version: 1.0 Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Archit Taneja The HDMI core IP on OMAP5 has a wider address range for registers. The offsets for the later registers can't fit into the u16 type currently used for hdmi register read and write functions. Use u32 for offsets instead. Signed-off-by: Archit Taneja Signed-off-by: Tomi Valkeinen --- drivers/video/fbdev/omap2/dss/hdmi.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/video/fbdev/omap2/dss/hdmi.h b/drivers/video/fbdev/omap2/dss/hdmi.h index d784b2cced9d..0e5979ef933c 100644 --- a/drivers/video/fbdev/omap2/dss/hdmi.h +++ b/drivers/video/fbdev/omap2/dss/hdmi.h @@ -361,13 +361,13 @@ struct hdmi_core_data { struct hdmi_core_infoframe_avi avi_cfg; }; -static inline void hdmi_write_reg(void __iomem *base_addr, const u16 idx, +static inline void hdmi_write_reg(void __iomem *base_addr, const u32 idx, u32 val) { __raw_writel(val, base_addr + idx); } -static inline u32 hdmi_read_reg(void __iomem *base_addr, const u16 idx) +static inline u32 hdmi_read_reg(void __iomem *base_addr, const u32 idx) { return __raw_readl(base_addr + idx); }