From patchwork Thu May 8 20:16:51 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Belisko X-Patchwork-Id: 4138561 Return-Path: X-Original-To: patchwork-linux-fbdev@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id F02B69F387 for ; Thu, 8 May 2014 20:17:48 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2C1B8201FA for ; Thu, 8 May 2014 20:17:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 46C2C20212 for ; Thu, 8 May 2014 20:17:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755837AbaEHUR0 (ORCPT ); Thu, 8 May 2014 16:17:26 -0400 Received: from mail-ee0-f43.google.com ([74.125.83.43]:64289 "EHLO mail-ee0-f43.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755625AbaEHURY (ORCPT ); Thu, 8 May 2014 16:17:24 -0400 Received: by mail-ee0-f43.google.com with SMTP id d17so2059350eek.2 for ; Thu, 08 May 2014 13:17:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=ePGhUTxyeiJzMHsULxcrOByFgqbOpveN50RYhwFKo58=; b=SWzxsFwmgNzSfKmJ/i2GEIYr3IaXwyddTr8EL4P7CfKII8V15NIAd7q2BmWRNxsyTD /0E7vWR6M7qyA7oEJbOYC0nm0OVNhkljEyjtkbl9VWktkpRV+EgSfHaZ7sfGfWKsPwK+ fBYOweycRtVcwQMpyYmwlOcV6GYAFke0eyCXGFKDPc9vIfDWhawGCBFrphuTokEm7k6c Pk8gPSJBEKal+VatDzxgOOQ1kyk+dMRiOdiTuq+83fFdmKXClMod4ud4siP2waf1uReq rBGQnOiFFixqlxsyaWHnLkhbAKN4vEVWRj5D5a8+Z9+OVZYLyArbkUE/FNlR+tXp91gn 1XiQ== X-Received: by 10.14.32.136 with SMTP id o8mr8028755eea.35.1399580242175; Thu, 08 May 2014 13:17:22 -0700 (PDT) Received: from nb.lan (ip-85.163.252.10.o2inet.sk. [85.163.252.10]) by mx.google.com with ESMTPSA id cb5sm6469401eeb.18.2014.05.08.13.17.19 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 08 May 2014 13:17:21 -0700 (PDT) From: Marek Belisko To: robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, rdunlap@infradead.org, bcousson@baylibre.com, tony@atomide.com, linux@arm.linux.org.uk, plagnioj@jcrosoft.com, tomi.valkeinen@ti.com, grant.likely@linaro.org Cc: devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-fbdev@vger.kernel.org, hns@goldelico.com, Marek Belisko Subject: [PATCH v3 2/3] ARM: dts: oma3-gta04: Add display support Date: Thu, 8 May 2014 22:16:51 +0200 Message-Id: <1399580212-5183-3-git-send-email-marek@goldelico.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1399580212-5183-1-git-send-email-marek@goldelico.com> References: <1399580212-5183-1-git-send-email-marek@goldelico.com> Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_HI,RP_MATCHES_RCVD,T_DKIM_INVALID,UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch add support for lcd display on gta04 board. Display control is connected to spi (used spi bitbang driver). Signed-off-by: Marek Belisko Acked-by: Tony Lindgren --- arch/arm/boot/dts/omap3-gta04.dts | 87 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/arch/arm/boot/dts/omap3-gta04.dts b/arch/arm/boot/dts/omap3-gta04.dts index f8ad125..eb9ab1a 100644 --- a/arch/arm/boot/dts/omap3-gta04.dts +++ b/arch/arm/boot/dts/omap3-gta04.dts @@ -44,6 +44,36 @@ ti,mcbsp = <&mcbsp2>; ti,codec = <&twl_audio>; }; + + spi_lcd { + compatible = "spi-gpio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi_gpio_pins>; + + gpio-sck = <&gpio1 12 0>; + gpio-miso = <&gpio1 18 0>; + gpio-mosi = <&gpio1 20 0>; + cs-gpios = <&gpio1 19 0>; + num-chipselects = <1>; + + /* lcd panel */ + lcd: td028ttec1@0 { + compatible = "toppoly,td028ttec1"; + reg = <0>; + spi-max-frequency = <100000>; + spi-cpol; + spi-cpha; + + label = "lcd"; + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; + }; }; &omap3_pmx_core { @@ -78,6 +108,47 @@ 0x11e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ >; }; + + dss_dpi_pins: pinmux_dss_dpi_pins { + pinctrl-single,pins = < + 0x0a4 (PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ + 0x0a6 (PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ + 0x0a8 (PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ + 0x0aa (PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ + 0x0ac (PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ + 0x0ae (PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ + 0x0b0 (PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ + 0x0b2 (PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ + 0x0b4 (PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ + 0x0b6 (PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ + 0x0b8 (PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ + 0x0ba (PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ + 0x0bc (PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ + 0x0be (PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ + 0x0c0 (PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ + 0x0c2 (PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ + 0x0c4 (PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ + 0x0c6 (PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ + 0x0c8 (PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ + 0x0ca (PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ + 0x0cc (PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ + 0x0ce (PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ + 0x0d0 (PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ + 0x0d2 (PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ + 0x0d4 (PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ + 0x0d6 (PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ + 0x0d8 (PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ + 0x0da (PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ + >; + }; + + spi_gpio_pins: spi_gpio_pinmux { + pinctrl-single,pins = <0x5a8 (PIN_OUTPUT | MUX_MODE4) /* clk */ + 0x5b6 (PIN_OUTPUT | MUX_MODE4) /* cs */ + 0x5b8 (PIN_OUTPUT | MUX_MODE4) /* tx */ + 0x5b4 (PIN_INPUT | MUX_MODE4) /* rx */ + >; + }; }; &i2c1 { @@ -219,3 +290,19 @@ regulator-min-microvolt = <2800000>; regulator-max-microvolt = <3150000>; }; + +&dss { + pinctrl-names = "default"; + pinctrl-0 = < &dss_dpi_pins >; + + status = "okay"; + + vdds_dsi-supply = <&vpll2>; + + port { + dpi_out: endpoint { + remote-endpoint = <&lcd_in>; + data-lines = <24>; + }; + }; +};