From patchwork Thu Jul 3 13:46:39 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ian Abbott X-Patchwork-Id: 4473501 Return-Path: X-Original-To: patchwork-linux-fbdev@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 222C19F26C for ; Thu, 3 Jul 2014 13:48:02 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5FB2220381 for ; Thu, 3 Jul 2014 13:48:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8D121202F2 for ; Thu, 3 Jul 2014 13:47:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758043AbaGCNrQ (ORCPT ); Thu, 3 Jul 2014 09:47:16 -0400 Received: from mail.mev.co.uk ([62.49.15.74]:39931 "EHLO mail.mev.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758108AbaGCNrP (ORCPT ); Thu, 3 Jul 2014 09:47:15 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.mev.co.uk (Postfix) with ESMTP id 814871D02D; Thu, 3 Jul 2014 14:47:11 +0100 (BST) X-Virus-Scanned: Debian amavisd-new at mail.mev.co.uk Received: from mail.mev.co.uk ([127.0.0.1]) by localhost (mantis.mev.local [127.0.0.1]) (amavisd-new, port 10024) with LMTP id EkXf9GxE8-zd; Thu, 3 Jul 2014 14:46:58 +0100 (BST) Received: from gentoo-ija64.mev.local (gentoo-ija64.mev.local [10.0.0.24]) (Authenticated sender: abbotti) by mail.mev.co.uk (Postfix) with ESMTPSA id EF25A1D02C; Thu, 3 Jul 2014 14:46:57 +0100 (BST) From: Ian Abbott To: linux-fbdev@vger.kernel.org Cc: Jean-Christophe Plagniol-Villard , Tomi Valkeinen , linux-kernel@vger.kernel.org, Ian Abbott Subject: [PATCH] video: da8xx-fb: preserve display width when changing HSYNC Date: Thu, 3 Jul 2014 14:46:39 +0100 Message-Id: <1404395199-5726-1-git-send-email-abbotti@mev.co.uk> X-Mailer: git-send-email 2.0.0 Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP When looking at this driver for a client, I noticed the code that configures the HSYNC pulse clobbers the display width in the same register. It only preserves the MS part of the width in bit 3 and zeros the LS part of the width in bits 9 to 4. This doesn't matter during initialization as the width is configured afterwards, but subsequent use of the FBIPUT_HSYNC ioctl would clobber the width. Preserve bits 9 to 0 of LCD_RASTER_TIMING_0_REG when configuring the horizontal sync. Signed-off-by: Ian Abbott --- I haven't tested this change, but it's pretty trivial. --- drivers/video/fbdev/da8xx-fb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/video/fbdev/da8xx-fb.c b/drivers/video/fbdev/da8xx-fb.c index 788f6b3..10c876c 100644 --- a/drivers/video/fbdev/da8xx-fb.c +++ b/drivers/video/fbdev/da8xx-fb.c @@ -419,7 +419,7 @@ static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width, { u32 reg; - reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf; + reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0x3ff; reg |= (((back_porch-1) & 0xff) << 24) | (((front_porch-1) & 0xff) << 16) | (((pulse_width-1) & 0x3f) << 10);