From patchwork Wed Nov 12 11:52:07 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 5288261 Return-Path: X-Original-To: patchwork-linux-fbdev@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 5A2E3C11AD for ; Wed, 12 Nov 2014 11:52:58 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 7524920165 for ; Wed, 12 Nov 2014 11:52:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 76F2420155 for ; Wed, 12 Nov 2014 11:52:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752282AbaKLLwx (ORCPT ); Wed, 12 Nov 2014 06:52:53 -0500 Received: from devils.ext.ti.com ([198.47.26.153]:41984 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752201AbaKLLww (ORCPT ); Wed, 12 Nov 2014 06:52:52 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id sACBqpSj026176; Wed, 12 Nov 2014 05:52:51 -0600 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id sACBqp8q026412; Wed, 12 Nov 2014 05:52:51 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.174.1; Wed, 12 Nov 2014 05:52:52 -0600 Received: from deskari.lan (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id sACBqgI2031206; Wed, 12 Nov 2014 05:52:50 -0600 From: Tomi Valkeinen To: , CC: Tomi Valkeinen Subject: [PATCH 05/22] OMAPDSS: DSI: remove clkin from dsi_clock_info Date: Wed, 12 Nov 2014 13:52:07 +0200 Message-ID: <1415793144-11723-6-git-send-email-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.1.3 In-Reply-To: <1415793144-11723-1-git-send-email-tomi.valkeinen@ti.com> References: <1415793144-11723-1-git-send-email-tomi.valkeinen@ti.com> MIME-Version: 1.0 Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP struct dsi_clock_info contains clkin field, which is the rate of the PLL's input clock. This field is not needed, as it can be easily retrieved by using the clk_get_rate(). This patch removes the clkin field. Signed-off-by: Tomi Valkeinen --- drivers/video/fbdev/omap2/dss/dpi.c | 1 - drivers/video/fbdev/omap2/dss/dsi.c | 13 ++++--------- drivers/video/fbdev/omap2/dss/dss.h | 1 - 3 files changed, 4 insertions(+), 11 deletions(-) diff --git a/drivers/video/fbdev/omap2/dss/dpi.c b/drivers/video/fbdev/omap2/dss/dpi.c index aa095c4927ec..91f18ab72007 100644 --- a/drivers/video/fbdev/omap2/dss/dpi.c +++ b/drivers/video/fbdev/omap2/dss/dpi.c @@ -223,7 +223,6 @@ static bool dpi_dsi_clk_calc(struct dpi_data *dpi, unsigned long pck, ctx->dsidev = dpi->dsidev; ctx->pck_min = pck - 1000; ctx->pck_max = pck + 1000; - ctx->dsi_cinfo.clkin = clkin; pll_min = 0; pll_max = 0; diff --git a/drivers/video/fbdev/omap2/dss/dsi.c b/drivers/video/fbdev/omap2/dss/dsi.c index 1c5a15581669..deab4135ddc0 100644 --- a/drivers/video/fbdev/omap2/dss/dsi.c +++ b/drivers/video/fbdev/omap2/dss/dsi.c @@ -1486,8 +1486,7 @@ static int dsi_calc_clock_rates(struct platform_device *dsidev, if (cinfo->regm_dsi > dsi->regm_dsi_max) return -EINVAL; - cinfo->clkin = clk_get_rate(dsi->sys_clk); - cinfo->fint = cinfo->clkin / cinfo->regn; + cinfo->fint = clk_get_rate(dsi->sys_clk) / cinfo->regn; if (cinfo->fint > dsi->fint_max || cinfo->fint < dsi->fint_min) return -EINVAL; @@ -1548,7 +1547,6 @@ int dsi_pll_set_clock_div(struct platform_device *dsidev, DSSDBG("DSI PLL clock config starts"); - dsi->current_cinfo.clkin = cinfo->clkin; dsi->current_cinfo.fint = cinfo->fint; dsi->current_cinfo.clkin4ddr = cinfo->clkin4ddr; dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk = @@ -1563,13 +1561,13 @@ int dsi_pll_set_clock_div(struct platform_device *dsidev, DSSDBG("DSI Fint %ld\n", cinfo->fint); - DSSDBG("clkin rate %ld\n", cinfo->clkin); + DSSDBG("clkin rate %ld\n", clk_get_rate(dsi->sys_clk)); /* DSIPHY == CLKIN4DDR */ DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu = %lu\n", cinfo->regm, cinfo->regn, - cinfo->clkin, + clk_get_rate(dsi->sys_clk), cinfo->clkin4ddr); DSSDBG("Data rate on 1 DSI lane %ld Mbps\n", @@ -1771,7 +1769,7 @@ static void dsi_dump_dsidev_clocks(struct platform_device *dsidev, seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1); - seq_printf(s, "dsi pll clkin\t%lu\n", cinfo->clkin); + seq_printf(s, "dsi pll clkin\t%lu\n", clk_get_rate(dsi->sys_clk)); seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn); @@ -4780,7 +4778,6 @@ static bool dsi_cm_calc(struct dsi_data *dsi, ctx->req_pck_min = pck; ctx->req_pck_nom = pck; ctx->req_pck_max = pck * 3 / 2; - ctx->dsi_cinfo.clkin = clkin; pll_min = max(cfg->hs_clk_min * 4, txbyteclk * 4 * 4); pll_max = cfg->hs_clk_max * 4; @@ -5066,8 +5063,6 @@ static bool dsi_vm_calc(struct dsi_data *dsi, ctx->dsidev = dsi->pdev; ctx->config = cfg; - ctx->dsi_cinfo.clkin = clkin; - /* these limits should come from the panel driver */ ctx->req_pck_min = t->pixelclock - 1000; ctx->req_pck_nom = t->pixelclock; diff --git a/drivers/video/fbdev/omap2/dss/dss.h b/drivers/video/fbdev/omap2/dss/dss.h index 712592d2e5f7..45e255ecff29 100644 --- a/drivers/video/fbdev/omap2/dss/dss.h +++ b/drivers/video/fbdev/omap2/dss/dss.h @@ -114,7 +114,6 @@ struct dsi_clock_info { /* rates that we get with dividers below */ unsigned long fint; unsigned long clkin4ddr; - unsigned long clkin; unsigned long dsi_pll_hsdiv_dispc_clk; /* OMAP3: DSI1_PLL_CLK * OMAP4: PLLx_CLK1 */ unsigned long dsi_pll_hsdiv_dsi_clk; /* OMAP3: DSI2_PLL_CLK