From patchwork Mon Jul 20 15:32:06 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Boris BREZILLON X-Patchwork-Id: 6828841 Return-Path: X-Original-To: patchwork-linux-fbdev@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 4416F9F358 for ; Mon, 20 Jul 2015 15:33:29 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 56A1220503 for ; Mon, 20 Jul 2015 15:33:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 45B1B20451 for ; Mon, 20 Jul 2015 15:33:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932561AbbGTPdH (ORCPT ); Mon, 20 Jul 2015 11:33:07 -0400 Received: from down.free-electrons.com ([37.187.137.238]:56259 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S932356AbbGTPcT (ORCPT ); Mon, 20 Jul 2015 11:32:19 -0400 Received: by mail.free-electrons.com (Postfix, from userid 106) id D9FDE1F41; Mon, 20 Jul 2015 17:32:22 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-8.1 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from localhost.localdomain (AToulouse-657-1-56-159.w82-125.abo.wanadoo.fr [82.125.234.159]) by mail.free-electrons.com (Postfix) with ESMTPSA id 1181523FD; Mon, 20 Jul 2015 17:32:22 +0200 (CEST) From: Boris Brezillon To: Thierry Reding , linux-pwm@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Bryan Wu , Richard Purdie , Jacek Anaszewski , linux-leds@vger.kernel.org, Heiko Stuebner , linux-rockchip@lists.infradead.org, Jingoo Han , Lee Jones , linux-fbdev@vger.kernel.org, Mark Brown , Liam Girdwood , Jean-Christophe Plagniol-Villard , Tomi Valkeinen , Doug Anderson , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Maxime Ripard , Boris Brezillon Subject: [PATCH v2 09/10] pwm: rockchip: add initial state retrieval Date: Mon, 20 Jul 2015 17:32:06 +0200 Message-Id: <1437406327-6207-10-git-send-email-boris.brezillon@free-electrons.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1437406327-6207-1-git-send-email-boris.brezillon@free-electrons.com> References: <1437406327-6207-1-git-send-email-boris.brezillon@free-electrons.com> Sender: linux-fbdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-fbdev@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Implement the ->reset_state() function to expose initial state. Signed-off-by: Boris Brezillon --- drivers/pwm/pwm-rockchip.c | 66 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 66 insertions(+) diff --git a/drivers/pwm/pwm-rockchip.c b/drivers/pwm/pwm-rockchip.c index 7d9cc90..6eab25c 100644 --- a/drivers/pwm/pwm-rockchip.c +++ b/drivers/pwm/pwm-rockchip.c @@ -51,6 +51,7 @@ struct rockchip_pwm_data { void (*set_enable)(struct pwm_chip *chip, struct pwm_device *pwm, bool enable); + void (*reset_state)(struct pwm_chip *chip, struct pwm_device *pwm); }; static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *c) @@ -75,6 +76,18 @@ static void rockchip_pwm_set_enable_v1(struct pwm_chip *chip, writel_relaxed(val, pc->base + pc->data->regs.ctrl); } +static void rockchip_pwm_reset_state_v1(struct pwm_chip *chip, + struct pwm_device *pwm) +{ + struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); + u32 enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN; + u32 val; + + val = readl(pc->base + pc->data->regs.ctrl); + if ((val & enable_conf) == enable_conf) + pwm->state.enabled = true; +} + static void rockchip_pwm_set_enable_v2(struct pwm_chip *chip, struct pwm_device *pwm, bool enable) { @@ -98,6 +111,54 @@ static void rockchip_pwm_set_enable_v2(struct pwm_chip *chip, writel_relaxed(val, pc->base + pc->data->regs.ctrl); } +static void rockchip_pwm_reset_state_v2(struct pwm_chip *chip, + struct pwm_device *pwm) +{ + struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); + u32 enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE | + PWM_CONTINUOUS; + u32 val; + + val = readl(pc->base + pc->data->regs.ctrl); + if ((val & enable_conf) != enable_conf) + return; + + pwm->state.enabled = true; + + if (!(val & PWM_DUTY_POSITIVE)) + pwm->state.polarity = PWM_POLARITY_INVERSED; +} + +static void rockchip_pwm_reset_state(struct pwm_chip *chip, + struct pwm_device *pwm) +{ + struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); + unsigned long clk_rate; + u64 tmp; + int ret; + + ret = clk_enable(pc->clk); + if (ret) + return; + + clk_rate = clk_get_rate(pc->clk); + + tmp = readl(pc->base + pc->data->regs.period); + tmp *= pc->data->prescaler * NSEC_PER_SEC; + do_div(tmp, clk_rate); + pwm->state.period = tmp; + + tmp = readl(pc->base + pc->data->regs.duty); + tmp *= pc->data->prescaler * NSEC_PER_SEC; + do_div(tmp, clk_rate); + pwm->state.duty_cycle = tmp; + + pc->data->reset_state(chip, chip->pwms); + + if (!pwm_is_enabled(pwm)) + clk_disable(pc->clk); +} + static int rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, int duty_ns, int period_ns) { @@ -171,6 +232,7 @@ static void rockchip_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) } static const struct pwm_ops rockchip_pwm_ops_v1 = { + .reset_state = rockchip_pwm_reset_state, .config = rockchip_pwm_config, .enable = rockchip_pwm_enable, .disable = rockchip_pwm_disable, @@ -178,6 +240,7 @@ static const struct pwm_ops rockchip_pwm_ops_v1 = { }; static const struct pwm_ops rockchip_pwm_ops_v2 = { + .reset_state = rockchip_pwm_reset_state, .config = rockchip_pwm_config, .set_polarity = rockchip_pwm_set_polarity, .enable = rockchip_pwm_enable, @@ -195,6 +258,7 @@ static const struct rockchip_pwm_data pwm_data_v1 = { .prescaler = 2, .ops = &rockchip_pwm_ops_v1, .set_enable = rockchip_pwm_set_enable_v1, + .reset_state = rockchip_pwm_reset_state_v1, }; static const struct rockchip_pwm_data pwm_data_v2 = { @@ -207,6 +271,7 @@ static const struct rockchip_pwm_data pwm_data_v2 = { .prescaler = 1, .ops = &rockchip_pwm_ops_v2, .set_enable = rockchip_pwm_set_enable_v2, + .reset_state = rockchip_pwm_reset_state_v2, }; static const struct rockchip_pwm_data pwm_data_vop = { @@ -219,6 +284,7 @@ static const struct rockchip_pwm_data pwm_data_vop = { .prescaler = 1, .ops = &rockchip_pwm_ops_v2, .set_enable = rockchip_pwm_set_enable_v2, + .reset_state = rockchip_pwm_reset_state_v2, }; static const struct of_device_id rockchip_pwm_dt_ids[] = {